2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
40 #include "hw/block/flash.h"
41 #include "block/block.h"
42 #include "qemu/timer.h"
43 #include "qemu/bitops.h"
44 #include "exec/address-spaces.h"
45 #include "qemu/host-utils.h"
46 #include "hw/sysbus.h"
48 #define PFLASH_BUG(fmt, ...) \
50 fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
54 /* #define PFLASH_DEBUG */
56 #define DPRINTF(fmt, ...) \
58 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
61 #define DPRINTF(fmt, ...) do { } while (0)
64 #define TYPE_CFI_PFLASH01 "cfi.pflash01"
65 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
69 SysBusDevice parent_obj
;
76 uint8_t device_width
; /* If 0, device width not specified. */
77 uint8_t max_device_width
; /* max device width in bytes */
79 uint8_t wcycle
; /* if 0, the flash is read normally */
88 uint8_t cfi_table
[0x52];
90 unsigned int writeblock_size
;
97 static const VMStateDescription vmstate_pflash
= {
98 .name
= "pflash_cfi01",
100 .minimum_version_id
= 1,
101 .fields
= (VMStateField
[]) {
102 VMSTATE_UINT8(wcycle
, pflash_t
),
103 VMSTATE_UINT8(cmd
, pflash_t
),
104 VMSTATE_UINT8(status
, pflash_t
),
105 VMSTATE_UINT64(counter
, pflash_t
),
106 VMSTATE_END_OF_LIST()
110 static void pflash_timer (void *opaque
)
112 pflash_t
*pfl
= opaque
;
114 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
117 memory_region_rom_device_set_romd(&pfl
->mem
, true);
122 /* Perform a CFI query based on the bank width of the flash.
123 * If this code is called we know we have a device_width set for
126 static uint32_t pflash_cfi_query(pflash_t
*pfl
, hwaddr offset
)
132 /* Adjust incoming offset to match expected device-width
133 * addressing. CFI query addresses are always specified in terms of
134 * the maximum supported width of the device. This means that x8
135 * devices and x8/x16 devices in x8 mode behave differently. For
136 * devices that are not used at their max width, we will be
137 * provided with addresses that use higher address bits than
138 * expected (based on the max width), so we will shift them lower
139 * so that they will match the addresses used when
140 * device_width==max_device_width.
142 boff
= offset
>> (ctz32(pfl
->bank_width
) +
143 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
145 if (boff
> pfl
->cfi_len
) {
148 /* Now we will construct the CFI response generated by a single
149 * device, then replicate that for all devices that make up the
150 * bus. For wide parts used in x8 mode, CFI query responses
151 * are different than native byte-wide parts.
153 resp
= pfl
->cfi_table
[boff
];
154 if (pfl
->device_width
!= pfl
->max_device_width
) {
155 /* The only case currently supported is x8 mode for a
158 if (pfl
->device_width
!= 1 || pfl
->bank_width
> 4) {
159 DPRINTF("%s: Unsupported device configuration: "
160 "device_width=%d, max_device_width=%d\n",
161 __func__
, pfl
->device_width
,
162 pfl
->max_device_width
);
165 /* CFI query data is repeated, rather than zero padded for
166 * wide devices used in x8 mode.
168 for (i
= 1; i
< pfl
->max_device_width
; i
++) {
169 resp
= deposit32(resp
, 8 * i
, 8, pfl
->cfi_table
[boff
]);
172 /* Replicate responses for each device in bank. */
173 if (pfl
->device_width
< pfl
->bank_width
) {
174 for (i
= pfl
->device_width
;
175 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
176 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
185 /* Perform a device id query based on the bank width of the flash. */
186 static uint32_t pflash_devid_query(pflash_t
*pfl
, hwaddr offset
)
192 /* Adjust incoming offset to match expected device-width
193 * addressing. Device ID read addresses are always specified in
194 * terms of the maximum supported width of the device. This means
195 * that x8 devices and x8/x16 devices in x8 mode behave
196 * differently. For devices that are not used at their max width,
197 * we will be provided with addresses that use higher address bits
198 * than expected (based on the max width), so we will shift them
199 * lower so that they will match the addresses used when
200 * device_width==max_device_width.
202 boff
= offset
>> (ctz32(pfl
->bank_width
) +
203 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
205 /* Mask off upper bits which may be used in to query block
206 * or sector lock status at other addresses.
207 * Offsets 2/3 are block lock status, is not emulated.
209 switch (boff
& 0xFF) {
212 DPRINTF("%s: Manufacturer Code %04x\n", __func__
, ret
);
216 DPRINTF("%s: Device ID Code %04x\n", __func__
, ret
);
219 DPRINTF("%s: Read Device Information offset=%x\n", __func__
,
224 /* Replicate responses for each device in bank. */
225 if (pfl
->device_width
< pfl
->bank_width
) {
226 for (i
= pfl
->device_width
;
227 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
228 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
235 static uint32_t pflash_read (pflash_t
*pfl
, hwaddr offset
,
245 DPRINTF("%s: reading offset " TARGET_FMT_plx
" under cmd %02x width %d\n",
246 __func__
, offset
, pfl
->cmd
, width
);
250 /* This should never happen : reset state & treat it as a read */
251 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
254 /* fall through to read code */
256 /* Flash area read */
261 DPRINTF("%s: data offset " TARGET_FMT_plx
" %02x\n",
262 __func__
, offset
, ret
);
266 ret
= p
[offset
] << 8;
267 ret
|= p
[offset
+ 1];
270 ret
|= p
[offset
+ 1] << 8;
272 DPRINTF("%s: data offset " TARGET_FMT_plx
" %04x\n",
273 __func__
, offset
, ret
);
277 ret
= p
[offset
] << 24;
278 ret
|= p
[offset
+ 1] << 16;
279 ret
|= p
[offset
+ 2] << 8;
280 ret
|= p
[offset
+ 3];
283 ret
|= p
[offset
+ 1] << 8;
284 ret
|= p
[offset
+ 2] << 16;
285 ret
|= p
[offset
+ 3] << 24;
287 DPRINTF("%s: data offset " TARGET_FMT_plx
" %08x\n",
288 __func__
, offset
, ret
);
291 DPRINTF("BUG in %s\n", __func__
);
295 case 0x10: /* Single byte program */
296 case 0x20: /* Block erase */
297 case 0x28: /* Block erase */
298 case 0x40: /* single byte program */
299 case 0x50: /* Clear status register */
300 case 0x60: /* Block /un)lock */
301 case 0x70: /* Status Register */
302 case 0xe8: /* Write block */
303 /* Status register read. Return status from each device in
307 if (pfl
->device_width
&& width
> pfl
->device_width
) {
308 int shift
= pfl
->device_width
* 8;
309 while (shift
+ pfl
->device_width
* 8 <= width
* 8) {
310 ret
|= pfl
->status
<< shift
;
311 shift
+= pfl
->device_width
* 8;
313 } else if (!pfl
->device_width
&& width
> 2) {
314 /* Handle 32 bit flash cases where device width is not
315 * set. (Existing behavior before device width added.)
317 ret
|= pfl
->status
<< 16;
319 DPRINTF("%s: status %x\n", __func__
, ret
);
322 if (!pfl
->device_width
) {
323 /* Preserve old behavior if device width not specified */
324 boff
= offset
& 0xFF;
325 if (pfl
->bank_width
== 2) {
327 } else if (pfl
->bank_width
== 4) {
333 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
334 DPRINTF("%s: Manufacturer Code %04x\n", __func__
, ret
);
337 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
338 DPRINTF("%s: Device ID Code %04x\n", __func__
, ret
);
341 DPRINTF("%s: Read Device Information boff=%x\n", __func__
,
347 /* If we have a read larger than the bank_width, combine multiple
348 * manufacturer/device ID queries into a single response.
351 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
352 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
353 pflash_devid_query(pfl
,
354 offset
+ i
* pfl
->bank_width
));
358 case 0x98: /* Query mode */
359 if (!pfl
->device_width
) {
360 /* Preserve old behavior if device width not specified */
361 boff
= offset
& 0xFF;
362 if (pfl
->bank_width
== 2) {
364 } else if (pfl
->bank_width
== 4) {
368 if (boff
> pfl
->cfi_len
) {
371 ret
= pfl
->cfi_table
[boff
];
374 /* If we have a read larger than the bank_width, combine multiple
375 * CFI queries into a single response.
378 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
379 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
380 pflash_cfi_query(pfl
,
381 offset
+ i
* pfl
->bank_width
));
390 /* update flash content on disk */
391 static void pflash_update(pflash_t
*pfl
, int offset
,
396 offset_end
= offset
+ size
;
397 /* round to sectors */
398 offset
= offset
>> 9;
399 offset_end
= (offset_end
+ 511) >> 9;
400 bdrv_write(pfl
->bs
, offset
, pfl
->storage
+ (offset
<< 9),
401 offset_end
- offset
);
405 static inline void pflash_data_write(pflash_t
*pfl
, hwaddr offset
,
406 uint32_t value
, int width
, int be
)
408 uint8_t *p
= pfl
->storage
;
410 DPRINTF("%s: block write offset " TARGET_FMT_plx
411 " value %x counter %016" PRIx64
"\n",
412 __func__
, offset
, value
, pfl
->counter
);
419 p
[offset
] = value
>> 8;
420 p
[offset
+ 1] = value
;
423 p
[offset
+ 1] = value
>> 8;
428 p
[offset
] = value
>> 24;
429 p
[offset
+ 1] = value
>> 16;
430 p
[offset
+ 2] = value
>> 8;
431 p
[offset
+ 3] = value
;
434 p
[offset
+ 1] = value
>> 8;
435 p
[offset
+ 2] = value
>> 16;
436 p
[offset
+ 3] = value
>> 24;
443 static void pflash_write(pflash_t
*pfl
, hwaddr offset
,
444 uint32_t value
, int width
, int be
)
451 DPRINTF("%s: writing offset " TARGET_FMT_plx
" value %08x width %d wcycle 0x%x\n",
452 __func__
, offset
, value
, width
, pfl
->wcycle
);
455 /* Set the device in I/O access mode */
456 memory_region_rom_device_set_romd(&pfl
->mem
, false);
459 switch (pfl
->wcycle
) {
465 case 0x10: /* Single Byte Program */
466 case 0x40: /* Single Byte Program */
467 DPRINTF("%s: Single Byte Program\n", __func__
);
469 case 0x20: /* Block erase */
471 offset
&= ~(pfl
->sector_len
- 1);
473 DPRINTF("%s: block erase at " TARGET_FMT_plx
" bytes %x\n",
474 __func__
, offset
, (unsigned)pfl
->sector_len
);
477 memset(p
+ offset
, 0xff, pfl
->sector_len
);
478 pflash_update(pfl
, offset
, pfl
->sector_len
);
480 pfl
->status
|= 0x20; /* Block erase error */
482 pfl
->status
|= 0x80; /* Ready! */
484 case 0x50: /* Clear status bits */
485 DPRINTF("%s: Clear status bits\n", __func__
);
488 case 0x60: /* Block (un)lock */
489 DPRINTF("%s: Block unlock\n", __func__
);
491 case 0x70: /* Status Register */
492 DPRINTF("%s: Read status register\n", __func__
);
495 case 0x90: /* Read Device ID */
496 DPRINTF("%s: Read Device information\n", __func__
);
499 case 0x98: /* CFI query */
500 DPRINTF("%s: CFI query\n", __func__
);
502 case 0xe8: /* Write to buffer */
503 DPRINTF("%s: Write to buffer\n", __func__
);
504 pfl
->status
|= 0x80; /* Ready! */
506 case 0xf0: /* Probe for AMD flash */
507 DPRINTF("%s: Probe for AMD flash\n", __func__
);
509 case 0xff: /* Read array mode */
510 DPRINTF("%s: Read array mode\n", __func__
);
520 case 0x10: /* Single Byte Program */
521 case 0x40: /* Single Byte Program */
522 DPRINTF("%s: Single Byte Program\n", __func__
);
524 pflash_data_write(pfl
, offset
, value
, width
, be
);
525 pflash_update(pfl
, offset
, width
);
527 pfl
->status
|= 0x10; /* Programming error */
529 pfl
->status
|= 0x80; /* Ready! */
532 case 0x20: /* Block erase */
534 if (cmd
== 0xd0) { /* confirm */
537 } else if (cmd
== 0xff) { /* read array mode */
544 /* Mask writeblock size based on device width, or bank width if
545 * device width not specified.
547 if (pfl
->device_width
) {
548 value
= extract32(value
, 0, pfl
->device_width
* 8);
550 value
= extract32(value
, 0, pfl
->bank_width
* 8);
552 DPRINTF("%s: block write of %x bytes\n", __func__
, value
);
553 pfl
->counter
= value
;
560 } else if (cmd
== 0x01) {
563 } else if (cmd
== 0xff) {
566 DPRINTF("%s: Unknown (un)locking command\n", __func__
);
574 DPRINTF("%s: leaving query mode\n", __func__
);
583 case 0xe8: /* Block write */
585 pflash_data_write(pfl
, offset
, value
, width
, be
);
587 pfl
->status
|= 0x10; /* Programming error */
593 hwaddr mask
= pfl
->writeblock_size
- 1;
596 DPRINTF("%s: block write finished\n", __func__
);
599 /* Flush the entire write buffer onto backing storage. */
600 pflash_update(pfl
, offset
& mask
, pfl
->writeblock_size
);
602 pfl
->status
|= 0x10; /* Programming error */
612 case 3: /* Confirm mode */
614 case 0xe8: /* Block write */
619 DPRINTF("%s: unknown command for \"write block\"\n", __func__
);
620 PFLASH_BUG("Write block confirm");
629 /* Should never happen */
630 DPRINTF("%s: invalid write state\n", __func__
);
636 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
637 "(offset " TARGET_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
638 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
641 memory_region_rom_device_set_romd(&pfl
->mem
, true);
648 static uint32_t pflash_readb_be(void *opaque
, hwaddr addr
)
650 return pflash_read(opaque
, addr
, 1, 1);
653 static uint32_t pflash_readb_le(void *opaque
, hwaddr addr
)
655 return pflash_read(opaque
, addr
, 1, 0);
658 static uint32_t pflash_readw_be(void *opaque
, hwaddr addr
)
660 pflash_t
*pfl
= opaque
;
662 return pflash_read(pfl
, addr
, 2, 1);
665 static uint32_t pflash_readw_le(void *opaque
, hwaddr addr
)
667 pflash_t
*pfl
= opaque
;
669 return pflash_read(pfl
, addr
, 2, 0);
672 static uint32_t pflash_readl_be(void *opaque
, hwaddr addr
)
674 pflash_t
*pfl
= opaque
;
676 return pflash_read(pfl
, addr
, 4, 1);
679 static uint32_t pflash_readl_le(void *opaque
, hwaddr addr
)
681 pflash_t
*pfl
= opaque
;
683 return pflash_read(pfl
, addr
, 4, 0);
686 static void pflash_writeb_be(void *opaque
, hwaddr addr
,
689 pflash_write(opaque
, addr
, value
, 1, 1);
692 static void pflash_writeb_le(void *opaque
, hwaddr addr
,
695 pflash_write(opaque
, addr
, value
, 1, 0);
698 static void pflash_writew_be(void *opaque
, hwaddr addr
,
701 pflash_t
*pfl
= opaque
;
703 pflash_write(pfl
, addr
, value
, 2, 1);
706 static void pflash_writew_le(void *opaque
, hwaddr addr
,
709 pflash_t
*pfl
= opaque
;
711 pflash_write(pfl
, addr
, value
, 2, 0);
714 static void pflash_writel_be(void *opaque
, hwaddr addr
,
717 pflash_t
*pfl
= opaque
;
719 pflash_write(pfl
, addr
, value
, 4, 1);
722 static void pflash_writel_le(void *opaque
, hwaddr addr
,
725 pflash_t
*pfl
= opaque
;
727 pflash_write(pfl
, addr
, value
, 4, 0);
730 static const MemoryRegionOps pflash_cfi01_ops_be
= {
732 .read
= { pflash_readb_be
, pflash_readw_be
, pflash_readl_be
, },
733 .write
= { pflash_writeb_be
, pflash_writew_be
, pflash_writel_be
, },
735 .endianness
= DEVICE_NATIVE_ENDIAN
,
738 static const MemoryRegionOps pflash_cfi01_ops_le
= {
740 .read
= { pflash_readb_le
, pflash_readw_le
, pflash_readl_le
, },
741 .write
= { pflash_writeb_le
, pflash_writew_le
, pflash_writel_le
, },
743 .endianness
= DEVICE_NATIVE_ENDIAN
,
746 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
748 pflash_t
*pfl
= CFI_PFLASH01(dev
);
751 uint64_t blocks_per_device
, device_len
;
754 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
756 /* These are only used to expose the parameters of each device
757 * in the cfi_table[].
759 num_devices
= pfl
->device_width
? (pfl
->bank_width
/ pfl
->device_width
) : 1;
760 blocks_per_device
= pfl
->nb_blocs
/ num_devices
;
761 device_len
= pfl
->sector_len
* blocks_per_device
;
763 /* XXX: to be fixed */
765 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
766 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
770 memory_region_init_rom_device(
771 &pfl
->mem
, OBJECT(dev
),
772 pfl
->be
? &pflash_cfi01_ops_be
: &pflash_cfi01_ops_le
, pfl
,
773 pfl
->name
, total_len
);
774 vmstate_register_ram(&pfl
->mem
, DEVICE(pfl
));
775 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
776 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
779 /* read the initial flash content */
780 ret
= bdrv_read(pfl
->bs
, 0, pfl
->storage
, total_len
>> 9);
783 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
784 memory_region_destroy(&pfl
->mem
);
785 error_setg(errp
, "failed to read the initial flash content");
791 pfl
->ro
= bdrv_is_read_only(pfl
->bs
);
796 /* Default to devices being used at their maximum device width. This was
797 * assumed before the device_width support was added.
799 if (!pfl
->max_device_width
) {
800 pfl
->max_device_width
= pfl
->device_width
;
803 pfl
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, pflash_timer
, pfl
);
807 /* Hardcoded CFI table */
809 /* Standard "QRY" string */
810 pfl
->cfi_table
[0x10] = 'Q';
811 pfl
->cfi_table
[0x11] = 'R';
812 pfl
->cfi_table
[0x12] = 'Y';
813 /* Command set (Intel) */
814 pfl
->cfi_table
[0x13] = 0x01;
815 pfl
->cfi_table
[0x14] = 0x00;
816 /* Primary extended table address (none) */
817 pfl
->cfi_table
[0x15] = 0x31;
818 pfl
->cfi_table
[0x16] = 0x00;
819 /* Alternate command set (none) */
820 pfl
->cfi_table
[0x17] = 0x00;
821 pfl
->cfi_table
[0x18] = 0x00;
822 /* Alternate extended table (none) */
823 pfl
->cfi_table
[0x19] = 0x00;
824 pfl
->cfi_table
[0x1A] = 0x00;
826 pfl
->cfi_table
[0x1B] = 0x45;
828 pfl
->cfi_table
[0x1C] = 0x55;
829 /* Vpp min (no Vpp pin) */
830 pfl
->cfi_table
[0x1D] = 0x00;
831 /* Vpp max (no Vpp pin) */
832 pfl
->cfi_table
[0x1E] = 0x00;
834 pfl
->cfi_table
[0x1F] = 0x07;
835 /* Timeout for min size buffer write */
836 pfl
->cfi_table
[0x20] = 0x07;
837 /* Typical timeout for block erase */
838 pfl
->cfi_table
[0x21] = 0x0a;
839 /* Typical timeout for full chip erase (4096 ms) */
840 pfl
->cfi_table
[0x22] = 0x00;
842 pfl
->cfi_table
[0x23] = 0x04;
843 /* Max timeout for buffer write */
844 pfl
->cfi_table
[0x24] = 0x04;
845 /* Max timeout for block erase */
846 pfl
->cfi_table
[0x25] = 0x04;
847 /* Max timeout for chip erase */
848 pfl
->cfi_table
[0x26] = 0x00;
850 pfl
->cfi_table
[0x27] = ctz32(device_len
); /* + 1; */
851 /* Flash device interface (8 & 16 bits) */
852 pfl
->cfi_table
[0x28] = 0x02;
853 pfl
->cfi_table
[0x29] = 0x00;
854 /* Max number of bytes in multi-bytes write */
855 if (pfl
->bank_width
== 1) {
856 pfl
->cfi_table
[0x2A] = 0x08;
858 pfl
->cfi_table
[0x2A] = 0x0B;
860 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
862 pfl
->cfi_table
[0x2B] = 0x00;
863 /* Number of erase block regions (uniform) */
864 pfl
->cfi_table
[0x2C] = 0x01;
865 /* Erase block region 1 */
866 pfl
->cfi_table
[0x2D] = blocks_per_device
- 1;
867 pfl
->cfi_table
[0x2E] = (blocks_per_device
- 1) >> 8;
868 pfl
->cfi_table
[0x2F] = pfl
->sector_len
>> 8;
869 pfl
->cfi_table
[0x30] = pfl
->sector_len
>> 16;
872 pfl
->cfi_table
[0x31] = 'P';
873 pfl
->cfi_table
[0x32] = 'R';
874 pfl
->cfi_table
[0x33] = 'I';
876 pfl
->cfi_table
[0x34] = '1';
877 pfl
->cfi_table
[0x35] = '0';
879 pfl
->cfi_table
[0x36] = 0x00;
880 pfl
->cfi_table
[0x37] = 0x00;
881 pfl
->cfi_table
[0x38] = 0x00;
882 pfl
->cfi_table
[0x39] = 0x00;
884 pfl
->cfi_table
[0x3a] = 0x00;
886 pfl
->cfi_table
[0x3b] = 0x00;
887 pfl
->cfi_table
[0x3c] = 0x00;
889 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
892 static Property pflash_cfi01_properties
[] = {
893 DEFINE_PROP_DRIVE("drive", struct pflash_t
, bs
),
894 /* num-blocks is the number of blocks actually visible to the guest,
895 * ie the total size of the device divided by the sector length.
896 * If we're emulating flash devices wired in parallel the actual
897 * number of blocks per indvidual device will differ.
899 DEFINE_PROP_UINT32("num-blocks", struct pflash_t
, nb_blocs
, 0),
900 DEFINE_PROP_UINT64("sector-length", struct pflash_t
, sector_len
, 0),
901 /* width here is the overall width of this QEMU device in bytes.
902 * The QEMU device may be emulating a number of flash devices
903 * wired up in parallel; the width of each individual flash
904 * device should be specified via device-width. If the individual
905 * devices have a maximum width which is greater than the width
906 * they are being used for, this maximum width should be set via
907 * max-device-width (which otherwise defaults to device-width).
908 * So for instance a 32-bit wide QEMU flash device made from four
909 * 16-bit flash devices used in 8-bit wide mode would be configured
910 * with width = 4, device-width = 1, max-device-width = 2.
912 * If device-width is not specified we default to backwards
913 * compatible behaviour which is a bad emulation of two
914 * 16 bit devices making up a 32 bit wide QEMU device. This
915 * is deprecated for new uses of this device.
917 DEFINE_PROP_UINT8("width", struct pflash_t
, bank_width
, 0),
918 DEFINE_PROP_UINT8("device-width", struct pflash_t
, device_width
, 0),
919 DEFINE_PROP_UINT8("max-device-width", struct pflash_t
, max_device_width
, 0),
920 DEFINE_PROP_UINT8("big-endian", struct pflash_t
, be
, 0),
921 DEFINE_PROP_UINT16("id0", struct pflash_t
, ident0
, 0),
922 DEFINE_PROP_UINT16("id1", struct pflash_t
, ident1
, 0),
923 DEFINE_PROP_UINT16("id2", struct pflash_t
, ident2
, 0),
924 DEFINE_PROP_UINT16("id3", struct pflash_t
, ident3
, 0),
925 DEFINE_PROP_STRING("name", struct pflash_t
, name
),
926 DEFINE_PROP_END_OF_LIST(),
929 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
931 DeviceClass
*dc
= DEVICE_CLASS(klass
);
933 dc
->realize
= pflash_cfi01_realize
;
934 dc
->props
= pflash_cfi01_properties
;
935 dc
->vmsd
= &vmstate_pflash
;
936 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
940 static const TypeInfo pflash_cfi01_info
= {
941 .name
= TYPE_CFI_PFLASH01
,
942 .parent
= TYPE_SYS_BUS_DEVICE
,
943 .instance_size
= sizeof(struct pflash_t
),
944 .class_init
= pflash_cfi01_class_init
,
947 static void pflash_cfi01_register_types(void)
949 type_register_static(&pflash_cfi01_info
);
952 type_init(pflash_cfi01_register_types
)
954 pflash_t
*pflash_cfi01_register(hwaddr base
,
955 DeviceState
*qdev
, const char *name
,
957 BlockDriverState
*bs
,
958 uint32_t sector_len
, int nb_blocs
,
959 int bank_width
, uint16_t id0
, uint16_t id1
,
960 uint16_t id2
, uint16_t id3
, int be
)
962 DeviceState
*dev
= qdev_create(NULL
, TYPE_CFI_PFLASH01
);
964 if (bs
&& qdev_prop_set_drive(dev
, "drive", bs
)) {
967 qdev_prop_set_uint32(dev
, "num-blocks", nb_blocs
);
968 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
969 qdev_prop_set_uint8(dev
, "width", bank_width
);
970 qdev_prop_set_uint8(dev
, "big-endian", !!be
);
971 qdev_prop_set_uint16(dev
, "id0", id0
);
972 qdev_prop_set_uint16(dev
, "id1", id1
);
973 qdev_prop_set_uint16(dev
, "id2", id2
);
974 qdev_prop_set_uint16(dev
, "id3", id3
);
975 qdev_prop_set_string(dev
, "name", name
);
976 qdev_init_nofail(dev
);
978 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
979 return CFI_PFLASH01(dev
);
982 MemoryRegion
*pflash_cfi01_get_memory(pflash_t
*fl
)