hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  16 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  17 #define PCI_FUNC_MAX            8
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 #define FMT_PCIBUS                      PRIx64
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 pcibus_t addr, pcibus_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef struct PCIIORegion {
  85     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87     pcibus_t size;
  88     pcibus_t filtered_size;
  89     uint8_t type;
  90     PCIMapIORegionFunc *map_func;
  91 } PCIIORegion;
  92
  93 #define PCI_ROM_SLOT 6
  94 #define PCI_NUM_REGIONS 7
  95
  96 #include "pci_regs.h"
  97
  98 /* PCI HEADER_TYPE */
  99 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 100
 101 /* Size of the standard PCI config header */
 102 #define PCI_CONFIG_HEADER_SIZE 0x40
 103 /* Size of the standard PCI config space */
 104 #define PCI_CONFIG_SPACE_SIZE 0x100
 105 /* Size of the standart PCIe config space: 4KB */
 106 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 107
 108 #define PCI_NUM_PINS 4 /* A-D */
 109
 110 /* Bits in cap_present field. */
 111 enum {
 112     QEMU_PCI_CAP_MSIX = 0x1,
 113     QEMU_PCI_CAP_EXPRESS = 0x2,
 114
 115     /* multifunction capable device */
 116 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        2
 117     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 118 };
 119
 120 struct PCIDevice {
 121     DeviceState qdev;
 122     /* PCI config space */
 123     uint8_t *config;
 124
 125     /* Used to enable config checks on load. Note that writeable bits are
 126      * never checked even if set in cmask. */
 127     uint8_t *cmask;
 128
 129     /* Used to implement R/W bytes */
 130     uint8_t *wmask;
 131
 132     /* Used to implement RW1C(Write 1 to Clear) bytes */
 133     uint8_t *w1cmask;
 134
 135     /* Used to allocate config space for capabilities. */
 136     uint8_t *used;
 137
 138     /* the following fields are read only */
 139     PCIBus *bus;
 140     uint32_t devfn;
 141     char name[64];
 142     PCIIORegion io_regions[PCI_NUM_REGIONS];
 143
 144     /* do not access the following fields */
 145     PCIConfigReadFunc *config_read;
 146     PCIConfigWriteFunc *config_write;
 147
 148     /* IRQ objects for the INTA-INTD pins.  */
 149     qemu_irq *irq;
 150
 151     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 152     uint8_t irq_state;
 153
 154     /* Capability bits */
 155     uint32_t cap_present;
 156
 157     /* Offset of MSI-X capability in config space */
 158     uint8_t msix_cap;
 159
 160     /* MSI-X entries */
 161     int msix_entries_nr;
 162
 163     /* Space to store MSIX table */
 164     uint8_t *msix_table_page;
 165     /* MMIO index used to map MSIX table and pending bit entries. */
 166     int msix_mmio_index;
 167     /* Reference-count for entries actually in use by driver. */
 168     unsigned *msix_entry_used;
 169     /* Region including the MSI-X table */
 170     uint32_t msix_bar_size;
 171     /* Version id needed for VMState */
 172     int32_t version_id;
 173
 174     /* Location of option rom */
 175     char *romfile;
 176     ram_addr_t rom_offset;
 177     uint32_t rom_bar;
 178 };
 179
 180 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 181                                int instance_size, int devfn,
 182                                PCIConfigReadFunc *config_read,
 183                                PCIConfigWriteFunc *config_write);
 184
 185 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 186                             pcibus_t size, uint8_t type,
 187                             PCIMapIORegionFunc *map_func);
 188
 189 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 190                        uint8_t offset, uint8_t size);
 191
 192 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 193
 194 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 195
 196 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 197
 198
 199 uint32_t pci_default_read_config(PCIDevice *d,
 200                                  uint32_t address, int len);
 201 void pci_default_write_config(PCIDevice *d,
 202                               uint32_t address, uint32_t val, int len);
 203 void pci_device_save(PCIDevice *s, QEMUFile *f);
 204 int pci_device_load(PCIDevice *s, QEMUFile *f);
 205
 206 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 207 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 208 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 209 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 210                          const char *name, int devfn_min);
 211 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 212 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 213                   void *irq_opaque, int nirq);
 214 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 215 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 216                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 217                          void *irq_opaque, int devfn_min, int nirq);
 218
 219 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 220
 221 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 222                         const char *default_devaddr);
 223 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 224                                const char *default_devaddr);
 225 int pci_bus_num(PCIBus *s);
 226 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 227 PCIBus *pci_find_root_bus(int domain);
 228 int pci_find_domain(const PCIBus *bus);
 229 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 230 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 231 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 232
 233 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 234                       unsigned int *slotp, unsigned int *funcp);
 235 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 236                      unsigned *slotp);
 237
 238 void do_pci_info_print(Monitor *mon, const QObject *data);
 239 void do_pci_info(Monitor *mon, QObject **ret_data);
 240 void pci_bridge_update_mappings(PCIBus *b);
 241
 242 bool pci_msi_enabled(PCIDevice *dev);
 243 void pci_msi_notify(PCIDevice *dev, unsigned int vector);
 244
 245 static inline void
 246 pci_set_byte(uint8_t *config, uint8_t val)
 247 {
 248     *config = val;
 249 }
 250
 251 static inline uint8_t
 252 pci_get_byte(const uint8_t *config)
 253 {
 254     return *config;
 255 }
 256
 257 static inline void
 258 pci_set_word(uint8_t *config, uint16_t val)
 259 {
 260     cpu_to_le16wu((uint16_t *)config, val);
 261 }
 262
 263 static inline uint16_t
 264 pci_get_word(const uint8_t *config)
 265 {
 266     return le16_to_cpupu((const uint16_t *)config);
 267 }
 268
 269 static inline void
 270 pci_set_long(uint8_t *config, uint32_t val)
 271 {
 272     cpu_to_le32wu((uint32_t *)config, val);
 273 }
 274
 275 static inline uint32_t
 276 pci_get_long(const uint8_t *config)
 277 {
 278     return le32_to_cpupu((const uint32_t *)config);
 279 }
 280
 281 static inline void
 282 pci_set_quad(uint8_t *config, uint64_t val)
 283 {
 284     cpu_to_le64w((uint64_t *)config, val);
 285 }
 286
 287 static inline uint64_t
 288 pci_get_quad(const uint8_t *config)
 289 {
 290     return le64_to_cpup((const uint64_t *)config);
 291 }
 292
 293 static inline void
 294 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 295 {
 296     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 297 }
 298
 299 static inline void
 300 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 301 {
 302     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 303 }
 304
 305 static inline void
 306 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 307 {
 308     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 309 }
 310
 311 static inline void
 312 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 313 {
 314     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 315 }
 316
 317 static inline void
 318 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 319 {
 320     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 321 }
 322
 323 static inline void
 324 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 325 {
 326     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 327 }
 328
 329 /*
 330  * helper functions to do bit mask operation on configuration space.
 331  * Just to set bit, use test-and-set and discard returned value.
 332  * Just to clear bit, use test-and-clear and discard returned value.
 333  * NOTE: They aren't atomic.
 334  */
 335 static inline uint8_t
 336 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 337 {
 338     uint8_t val = pci_get_byte(config);
 339     pci_set_byte(config, val & ~mask);
 340     return val & mask;
 341 }
 342
 343 static inline uint8_t
 344 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 345 {
 346     uint8_t val = pci_get_byte(config);
 347     pci_set_byte(config, val | mask);
 348     return val & mask;
 349 }
 350
 351 static inline uint16_t
 352 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 353 {
 354     uint16_t val = pci_get_word(config);
 355     pci_set_word(config, val & ~mask);
 356     return val & mask;
 357 }
 358
 359 static inline uint16_t
 360 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 361 {
 362     uint16_t val = pci_get_word(config);
 363     pci_set_word(config, val | mask);
 364     return val & mask;
 365 }
 366
 367 static inline uint32_t
 368 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 369 {
 370     uint32_t val = pci_get_long(config);
 371     pci_set_long(config, val & ~mask);
 372     return val & mask;
 373 }
 374
 375 static inline uint32_t
 376 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 377 {
 378     uint32_t val = pci_get_long(config);
 379     pci_set_long(config, val | mask);
 380     return val & mask;
 381 }
 382
 383 static inline uint64_t
 384 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 385 {
 386     uint64_t val = pci_get_quad(config);
 387     pci_set_quad(config, val & ~mask);
 388     return val & mask;
 389 }
 390
 391 static inline uint64_t
 392 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 393 {
 394     uint64_t val = pci_get_quad(config);
 395     pci_set_quad(config, val | mask);
 396     return val & mask;
 397 }
 398
 399 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 400 typedef struct {
 401     DeviceInfo qdev;
 402     pci_qdev_initfn init;
 403     PCIUnregisterFunc *exit;
 404     PCIConfigReadFunc *config_read;
 405     PCIConfigWriteFunc *config_write;
 406
 407     /*
 408      * pci-to-pci bridge or normal device.
 409      * This doesn't mean pci host switch.
 410      * When card bus bridge is supported, this would be enhanced.
 411      */
 412     int is_bridge;
 413
 414     /* pcie stuff */
 415     int is_express;   /* is this device pci express? */
 416
 417     /* rom bar */
 418     const char *romfile;
 419 } PCIDeviceInfo;
 420
 421 void pci_qdev_register(PCIDeviceInfo *info);
 422 void pci_qdev_register_many(PCIDeviceInfo *info);
 423
 424 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 425                                     const char *name);
 426 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 427                                            bool multifunction,
 428                                            const char *name);
 429 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 430 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 431
 432 static inline int pci_is_express(const PCIDevice *d)
 433 {
 434     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 435 }
 436
 437 static inline uint32_t pci_config_size(const PCIDevice *d)
 438 {
 439     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 440 }
 441
 442 /* These are not pci specific. Should move into a separate header.
 443  * Only pci.c uses them, so keep them here for now.
 444  */
 445
 446 /* Get last byte of a range from offset + length.
 447  * Undefined for ranges that wrap around 0. */
 448 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 449 {
 450     return offset + len - 1;
 451 }
 452
 453 /* Check whether a given range covers a given byte. */
 454 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 455                                     uint64_t byte)
 456 {
 457     return offset <= byte && byte <= range_get_last(offset, len);
 458 }
 459
 460 /* Check whether 2 given ranges overlap.
 461  * Undefined if ranges that wrap around 0. */
 462 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 463                                  uint64_t first2, uint64_t len2)
 464 {
 465     uint64_t last1 = range_get_last(first1, len1);
 466     uint64_t last2 = range_get_last(first2, len2);
 467
 468     return !(last2 < first1 || last1 < first2);
 469 }
 470
 471 #endif