2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "hw/arm/xlnx-zynqmp.h"
20 #include "hw/intc/arm_gic_common.h"
21 #include "exec/address-spaces.h"
23 #define GIC_NUM_SPI_INTR 160
25 #define ARM_PHYS_TIMER_PPI 30
26 #define ARM_VIRT_TIMER_PPI 27
28 #define GIC_BASE_ADDR 0xf9000000
29 #define GIC_DIST_ADDR 0xf9010000
30 #define GIC_CPU_ADDR 0xf9020000
33 #define SATA_ADDR 0xFD0C0000
34 #define SATA_NUM_PORTS 2
36 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
37 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
40 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
44 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
45 0xFF000000, 0xFF010000,
48 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
52 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
53 0xFF160000, 0xFF170000,
56 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
60 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
61 0xFF040000, 0xFF050000,
64 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
68 typedef struct XlnxZynqMPGICRegion
{
71 } XlnxZynqMPGICRegion
;
73 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
74 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
75 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
78 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
80 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
83 static void xlnx_zynqmp_init(Object
*obj
)
85 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
88 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
89 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
90 "cortex-a53-" TYPE_ARM_CPU
);
91 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
95 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
96 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
97 "cortex-r5-" TYPE_ARM_CPU
);
98 object_property_add_child(obj
, "rpu-cpu[*]", OBJECT(&s
->rpu_cpu
[i
]),
102 object_property_add_link(obj
, "ddr-ram", TYPE_MEMORY_REGION
,
103 (Object
**)&s
->ddr_ram
,
104 qdev_prop_allow_set_link_before_realize
,
105 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
107 object_initialize(&s
->gic
, sizeof(s
->gic
), TYPE_ARM_GIC
);
108 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
110 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
111 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
112 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
115 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
116 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
117 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
120 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
121 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
123 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
124 object_initialize(&s
->sdhci
[i
], sizeof(s
->sdhci
[i
]),
126 qdev_set_parent_bus(DEVICE(&s
->sdhci
[i
]),
127 sysbus_get_default());
130 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
131 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]),
133 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
137 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
139 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
140 MemoryRegion
*system_memory
= get_system_memory();
143 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
144 ram_addr_t ddr_low_size
, ddr_high_size
;
145 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
148 ram_size
= memory_region_size(s
->ddr_ram
);
150 /* Create the DDR Memory Regions. User friendly checks should happen at
153 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
154 /* The RAM size is above the maximum available for the low DDR.
155 * Create the high DDR memory region as well.
157 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
158 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
159 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
161 memory_region_init_alias(&s
->ddr_ram_high
, NULL
,
162 "ddr-ram-high", s
->ddr_ram
,
163 ddr_low_size
, ddr_high_size
);
164 memory_region_add_subregion(get_system_memory(),
165 XLNX_ZYNQMP_HIGH_RAM_START
,
168 /* RAM must be non-zero */
170 ddr_low_size
= ram_size
;
173 memory_region_init_alias(&s
->ddr_ram_low
, NULL
,
174 "ddr-ram-low", s
->ddr_ram
,
176 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
178 /* Create the four OCM banks */
179 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
180 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
182 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
183 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
184 vmstate_register_ram_global(&s
->ocm_ram
[i
]);
185 memory_region_add_subregion(get_system_memory(),
186 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
187 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
193 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
194 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
195 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS
);
196 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
198 error_propagate(errp
, err
);
201 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
202 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
203 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
204 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
205 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
206 uint32_t addr
= r
->address
;
209 sysbus_mmio_map(gic
, r
->region_index
, addr
);
211 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
212 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
214 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
215 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
216 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
217 memory_region_add_subregion(system_memory
, addr
, alias
);
221 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
225 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
226 "psci-conduit", &error_abort
);
228 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
229 if (strcmp(name
, boot_cpu
)) {
230 /* Secondary CPUs start in PSCI powered-down state */
231 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
232 "start-powered-off", &error_abort
);
234 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
238 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
239 "reset-cbar", &error_abort
);
240 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
243 error_propagate(errp
, err
);
247 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
248 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
250 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
251 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
252 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
253 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
254 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
255 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
258 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
261 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
262 if (strcmp(name
, boot_cpu
)) {
263 /* Secondary CPUs start in PSCI powered-down state */
264 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
265 "start-powered-off", &error_abort
);
267 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
271 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
273 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
276 error_propagate(errp
, err
);
281 if (!s
->boot_cpu_ptr
) {
282 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
286 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
287 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
290 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
291 NICInfo
*nd
= &nd_table
[i
];
294 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
295 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
297 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
299 error_propagate(errp
, err
);
302 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
303 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
304 gic_spi
[gem_intr
[i
]]);
307 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
308 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
310 error_propagate(errp
, err
);
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
315 gic_spi
[uart_intr
[i
]]);
318 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
320 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
322 error_propagate(errp
, err
);
326 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
327 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
329 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
332 object_property_set_bool(OBJECT(&s
->sdhci
[i
]), true,
335 error_propagate(errp
, err
);
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
340 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
341 gic_spi
[sdhci_intr
[i
]]);
342 /* Alias controller SD bus to the SoC itself */
343 bus_name
= g_strdup_printf("sd-bus%d", i
);
344 object_property_add_alias(OBJECT(s
), bus_name
,
345 OBJECT(&s
->sdhci
[i
]), "sd-bus",
350 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
353 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized", &err
);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
356 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
357 gic_spi
[spi_intr
[i
]]);
359 /* Alias controller SPI bus to the SoC itself */
360 bus_name
= g_strdup_printf("spi%d", i
);
361 object_property_add_alias(OBJECT(s
), bus_name
,
362 OBJECT(&s
->spi
[i
]), "spi0",
368 static Property xlnx_zynqmp_props
[] = {
369 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
370 DEFINE_PROP_END_OF_LIST()
373 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
375 DeviceClass
*dc
= DEVICE_CLASS(oc
);
377 dc
->props
= xlnx_zynqmp_props
;
378 dc
->realize
= xlnx_zynqmp_realize
;
381 * Reason: creates an ARM CPU, thus use after free(), see
382 * arm_cpu_class_init()
384 dc
->cannot_destroy_with_object_finalize_yet
= true;
387 static const TypeInfo xlnx_zynqmp_type_info
= {
388 .name
= TYPE_XLNX_ZYNQMP
,
389 .parent
= TYPE_DEVICE
,
390 .instance_size
= sizeof(XlnxZynqMPState
),
391 .instance_init
= xlnx_zynqmp_init
,
392 .class_init
= xlnx_zynqmp_class_init
,
395 static void xlnx_zynqmp_register_types(void)
397 type_register_static(&xlnx_zynqmp_type_info
);
400 type_init(xlnx_zynqmp_register_types
)