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KVM: target-ppc: Enable TM state migration
[qemu/cris-port.git] / target-i386 / kvm.c
blob4bf0ac9e76a082e43a1c58c86c5431ee01e16d93
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38
39 //#define DEBUG_KVM
40
41 #ifdef DEBUG_KVM
42 #define DPRINTF(fmt, ...) \
43 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
44 #else
45 #define DPRINTF(fmt, ...) \
46 do { } while (0)
47 #endif
48
49 #define MSR_KVM_WALL_CLOCK 0x11
50 #define MSR_KVM_SYSTEM_TIME 0x12
51
52 #ifndef BUS_MCEERR_AR
53 #define BUS_MCEERR_AR 4
54 #endif
55 #ifndef BUS_MCEERR_AO
56 #define BUS_MCEERR_AO 5
57 #endif
58
59 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
60 KVM_CAP_INFO(SET_TSS_ADDR),
61 KVM_CAP_INFO(EXT_CPUID),
62 KVM_CAP_INFO(MP_STATE),
63 KVM_CAP_LAST_INFO
64 };
65
66 static bool has_msr_star;
67 static bool has_msr_hsave_pa;
68 static bool has_msr_tsc_adjust;
69 static bool has_msr_tsc_deadline;
70 static bool has_msr_feature_control;
71 static bool has_msr_async_pf_en;
72 static bool has_msr_pv_eoi_en;
73 static bool has_msr_misc_enable;
74 static bool has_msr_bndcfgs;
75 static bool has_msr_kvm_steal_time;
76 static int lm_capable_kernel;
77 static bool has_msr_hv_hypercall;
78 static bool has_msr_hv_vapic;
79 static bool has_msr_hv_tsc;
80
81 static bool has_msr_architectural_pmu;
82 static uint32_t num_architectural_pmu_counters;
83
84 bool kvm_allows_irq0_override(void)
85 {
86 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
87 }
88
89 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
90 {
91 struct kvm_cpuid2 *cpuid;
92 int r, size;
93
94 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
95 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
96 cpuid->nent = max;
97 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
98 if (r == 0 && cpuid->nent >= max) {
99 r = -E2BIG;
100 }
101 if (r < 0) {
102 if (r == -E2BIG) {
103 g_free(cpuid);
104 return NULL;
105 } else {
106 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
107 strerror(-r));
108 exit(1);
109 }
110 }
111 return cpuid;
112 }
113
114 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
115 * for all entries.
116 */
117 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
118 {
119 struct kvm_cpuid2 *cpuid;
120 int max = 1;
121 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
122 max *= 2;
123 }
124 return cpuid;
125 }
126
127 static const struct kvm_para_features {
128 int cap;
129 int feature;
130 } para_features[] = {
131 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
132 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
133 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
134 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
135 };
136
137 static int get_para_features(KVMState *s)
138 {
139 int i, features = 0;
140
141 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
142 if (kvm_check_extension(s, para_features[i].cap)) {
143 features |= (1 << para_features[i].feature);
144 }
145 }
146
147 return features;
148 }
149
150
151 /* Returns the value for a specific register on the cpuid entry
152 */
153 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
154 {
155 uint32_t ret = 0;
156 switch (reg) {
157 case R_EAX:
158 ret = entry->eax;
159 break;
160 case R_EBX:
161 ret = entry->ebx;
162 break;
163 case R_ECX:
164 ret = entry->ecx;
165 break;
166 case R_EDX:
167 ret = entry->edx;
168 break;
169 }
170 return ret;
171 }
172
173 /* Find matching entry for function/index on kvm_cpuid2 struct
174 */
175 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
176 uint32_t function,
177 uint32_t index)
178 {
179 int i;
180 for (i = 0; i < cpuid->nent; ++i) {
181 if (cpuid->entries[i].function == function &&
182 cpuid->entries[i].index == index) {
183 return &cpuid->entries[i];
184 }
185 }
186 /* not found: */
187 return NULL;
188 }
189
190 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
191 uint32_t index, int reg)
192 {
193 struct kvm_cpuid2 *cpuid;
194 uint32_t ret = 0;
195 uint32_t cpuid_1_edx;
196 bool found = false;
197
198 cpuid = get_supported_cpuid(s);
199
200 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
201 if (entry) {
202 found = true;
203 ret = cpuid_entry_get_reg(entry, reg);
204 }
205
206 /* Fixups for the data returned by KVM, below */
207
208 if (function == 1 && reg == R_EDX) {
209 /* KVM before 2.6.30 misreports the following features */
210 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
211 } else if (function == 1 && reg == R_ECX) {
212 /* We can set the hypervisor flag, even if KVM does not return it on
213 * GET_SUPPORTED_CPUID
214 */
215 ret |= CPUID_EXT_HYPERVISOR;
216 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
217 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
218 * and the irqchip is in the kernel.
219 */
220 if (kvm_irqchip_in_kernel() &&
221 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
222 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
223 }
224
225 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
226 * without the in-kernel irqchip
227 */
228 if (!kvm_irqchip_in_kernel()) {
229 ret &= ~CPUID_EXT_X2APIC;
230 }
231 } else if (function == 0x80000001 && reg == R_EDX) {
232 /* On Intel, kvm returns cpuid according to the Intel spec,
233 * so add missing bits according to the AMD spec:
234 */
235 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
236 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
237 }
238
239 g_free(cpuid);
240
241 /* fallback for older kernels */
242 if ((function == KVM_CPUID_FEATURES) && !found) {
243 ret = get_para_features(s);
244 }
245
246 return ret;
247 }
248
249 typedef struct HWPoisonPage {
250 ram_addr_t ram_addr;
251 QLIST_ENTRY(HWPoisonPage) list;
252 } HWPoisonPage;
253
254 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
255 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
256
257 static void kvm_unpoison_all(void *param)
258 {
259 HWPoisonPage *page, *next_page;
260
261 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
262 QLIST_REMOVE(page, list);
263 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
264 g_free(page);
265 }
266 }
267
268 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
269 {
270 HWPoisonPage *page;
271
272 QLIST_FOREACH(page, &hwpoison_page_list, list) {
273 if (page->ram_addr == ram_addr) {
274 return;
275 }
276 }
277 page = g_malloc(sizeof(HWPoisonPage));
278 page->ram_addr = ram_addr;
279 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
280 }
281
282 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
283 int *max_banks)
284 {
285 int r;
286
287 r = kvm_check_extension(s, KVM_CAP_MCE);
288 if (r > 0) {
289 *max_banks = r;
290 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
291 }
292 return -ENOSYS;
293 }
294
295 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
296 {
297 CPUX86State *env = &cpu->env;
298 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
299 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
300 uint64_t mcg_status = MCG_STATUS_MCIP;
301
302 if (code == BUS_MCEERR_AR) {
303 status |= MCI_STATUS_AR | 0x134;
304 mcg_status |= MCG_STATUS_EIPV;
305 } else {
306 status |= 0xc0;
307 mcg_status |= MCG_STATUS_RIPV;
308 }
309 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
310 (MCM_ADDR_PHYS << 6) | 0xc,
311 cpu_x86_support_mca_broadcast(env) ?
312 MCE_INJECT_BROADCAST : 0);
313 }
314
315 static void hardware_memory_error(void)
316 {
317 fprintf(stderr, "Hardware memory error!\n");
318 exit(1);
319 }
320
321 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
322 {
323 X86CPU *cpu = X86_CPU(c);
324 CPUX86State *env = &cpu->env;
325 ram_addr_t ram_addr;
326 hwaddr paddr;
327
328 if ((env->mcg_cap & MCG_SER_P) && addr
329 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
330 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
331 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
332 fprintf(stderr, "Hardware memory error for memory used by "
333 "QEMU itself instead of guest system!\n");
334 /* Hope we are lucky for AO MCE */
335 if (code == BUS_MCEERR_AO) {
336 return 0;
337 } else {
338 hardware_memory_error();
339 }
340 }
341 kvm_hwpoison_page_add(ram_addr);
342 kvm_mce_inject(cpu, paddr, code);
343 } else {
344 if (code == BUS_MCEERR_AO) {
345 return 0;
346 } else if (code == BUS_MCEERR_AR) {
347 hardware_memory_error();
348 } else {
349 return 1;
350 }
351 }
352 return 0;
353 }
354
355 int kvm_arch_on_sigbus(int code, void *addr)
356 {
357 X86CPU *cpu = X86_CPU(first_cpu);
358
359 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
360 ram_addr_t ram_addr;
361 hwaddr paddr;
362
363 /* Hope we are lucky for AO MCE */
364 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
365 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
366 addr, &paddr)) {
367 fprintf(stderr, "Hardware memory error for memory used by "
368 "QEMU itself instead of guest system!: %p\n", addr);
369 return 0;
370 }
371 kvm_hwpoison_page_add(ram_addr);
372 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
373 } else {
374 if (code == BUS_MCEERR_AO) {
375 return 0;
376 } else if (code == BUS_MCEERR_AR) {
377 hardware_memory_error();
378 } else {
379 return 1;
380 }
381 }
382 return 0;
383 }
384
385 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
386 {
387 CPUX86State *env = &cpu->env;
388
389 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
390 unsigned int bank, bank_num = env->mcg_cap & 0xff;
391 struct kvm_x86_mce mce;
392
393 env->exception_injected = -1;
394
395 /*
396 * There must be at least one bank in use if an MCE is pending.
397 * Find it and use its values for the event injection.
398 */
399 for (bank = 0; bank < bank_num; bank++) {
400 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
401 break;
402 }
403 }
404 assert(bank < bank_num);
405
406 mce.bank = bank;
407 mce.status = env->mce_banks[bank * 4 + 1];
408 mce.mcg_status = env->mcg_status;
409 mce.addr = env->mce_banks[bank * 4 + 2];
410 mce.misc = env->mce_banks[bank * 4 + 3];
411
412 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
413 }
414 return 0;
415 }
416
417 static void cpu_update_state(void *opaque, int running, RunState state)
418 {
419 CPUX86State *env = opaque;
420
421 if (running) {
422 env->tsc_valid = false;
423 }
424 }
425
426 unsigned long kvm_arch_vcpu_id(CPUState *cs)
427 {
428 X86CPU *cpu = X86_CPU(cs);
429 return cpu->env.cpuid_apic_id;
430 }
431
432 #ifndef KVM_CPUID_SIGNATURE_NEXT
433 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
434 #endif
435
436 static bool hyperv_hypercall_available(X86CPU *cpu)
437 {
438 return cpu->hyperv_vapic ||
439 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
440 }
441
442 static bool hyperv_enabled(X86CPU *cpu)
443 {
444 CPUState *cs = CPU(cpu);
445 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
446 (hyperv_hypercall_available(cpu) ||
447 cpu->hyperv_time ||
448 cpu->hyperv_relaxed_timing);
449 }
450
451 #define KVM_MAX_CPUID_ENTRIES 100
452
453 int kvm_arch_init_vcpu(CPUState *cs)
454 {
455 struct {
456 struct kvm_cpuid2 cpuid;
457 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
458 } QEMU_PACKED cpuid_data;
459 X86CPU *cpu = X86_CPU(cs);
460 CPUX86State *env = &cpu->env;
461 uint32_t limit, i, j, cpuid_i;
462 uint32_t unused;
463 struct kvm_cpuid_entry2 *c;
464 uint32_t signature[3];
465 int kvm_base = KVM_CPUID_SIGNATURE;
466 int r;
467
468 memset(&cpuid_data, 0, sizeof(cpuid_data));
469
470 cpuid_i = 0;
471
472 /* Paravirtualization CPUIDs */
473 if (hyperv_enabled(cpu)) {
474 c = &cpuid_data.entries[cpuid_i++];
475 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
476 memcpy(signature, "Microsoft Hv", 12);
477 c->eax = HYPERV_CPUID_MIN;
478 c->ebx = signature[0];
479 c->ecx = signature[1];
480 c->edx = signature[2];
481
482 c = &cpuid_data.entries[cpuid_i++];
483 c->function = HYPERV_CPUID_INTERFACE;
484 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
485 c->eax = signature[0];
486 c->ebx = 0;
487 c->ecx = 0;
488 c->edx = 0;
489
490 c = &cpuid_data.entries[cpuid_i++];
491 c->function = HYPERV_CPUID_VERSION;
492 c->eax = 0x00001bbc;
493 c->ebx = 0x00060001;
494
495 c = &cpuid_data.entries[cpuid_i++];
496 c->function = HYPERV_CPUID_FEATURES;
497 if (cpu->hyperv_relaxed_timing) {
498 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
499 }
500 if (cpu->hyperv_vapic) {
501 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
502 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
503 has_msr_hv_vapic = true;
504 }
505 if (cpu->hyperv_time &&
506 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
507 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
508 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
509 c->eax |= 0x200;
510 has_msr_hv_tsc = true;
511 }
512 c = &cpuid_data.entries[cpuid_i++];
513 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
514 if (cpu->hyperv_relaxed_timing) {
515 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
516 }
517 if (has_msr_hv_vapic) {
518 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
519 }
520 c->ebx = cpu->hyperv_spinlock_attempts;
521
522 c = &cpuid_data.entries[cpuid_i++];
523 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
524 c->eax = 0x40;
525 c->ebx = 0x40;
526
527 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
528 has_msr_hv_hypercall = true;
529 }
530
531 if (cpu->expose_kvm) {
532 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
533 c = &cpuid_data.entries[cpuid_i++];
534 c->function = KVM_CPUID_SIGNATURE | kvm_base;
535 c->eax = KVM_CPUID_FEATURES | kvm_base;
536 c->ebx = signature[0];
537 c->ecx = signature[1];
538 c->edx = signature[2];
539
540 c = &cpuid_data.entries[cpuid_i++];
541 c->function = KVM_CPUID_FEATURES | kvm_base;
542 c->eax = env->features[FEAT_KVM];
543
544 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
545
546 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
547
548 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
549 }
550
551 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
552
553 for (i = 0; i <= limit; i++) {
554 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
555 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
556 abort();
557 }
558 c = &cpuid_data.entries[cpuid_i++];
559
560 switch (i) {
561 case 2: {
562 /* Keep reading function 2 till all the input is received */
563 int times;
564
565 c->function = i;
566 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
567 KVM_CPUID_FLAG_STATE_READ_NEXT;
568 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
569 times = c->eax & 0xff;
570
571 for (j = 1; j < times; ++j) {
572 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
573 fprintf(stderr, "cpuid_data is full, no space for "
574 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
575 abort();
576 }
577 c = &cpuid_data.entries[cpuid_i++];
578 c->function = i;
579 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
580 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
581 }
582 break;
583 }
584 case 4:
585 case 0xb:
586 case 0xd:
587 for (j = 0; ; j++) {
588 if (i == 0xd && j == 64) {
589 break;
590 }
591 c->function = i;
592 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
593 c->index = j;
594 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
595
596 if (i == 4 && c->eax == 0) {
597 break;
598 }
599 if (i == 0xb && !(c->ecx & 0xff00)) {
600 break;
601 }
602 if (i == 0xd && c->eax == 0) {
603 continue;
604 }
605 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
606 fprintf(stderr, "cpuid_data is full, no space for "
607 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
608 abort();
609 }
610 c = &cpuid_data.entries[cpuid_i++];
611 }
612 break;
613 default:
614 c->function = i;
615 c->flags = 0;
616 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
617 break;
618 }
619 }
620
621 if (limit >= 0x0a) {
622 uint32_t ver;
623
624 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
625 if ((ver & 0xff) > 0) {
626 has_msr_architectural_pmu = true;
627 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
628
629 /* Shouldn't be more than 32, since that's the number of bits
630 * available in EBX to tell us _which_ counters are available.
631 * Play it safe.
632 */
633 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
634 num_architectural_pmu_counters = MAX_GP_COUNTERS;
635 }
636 }
637 }
638
639 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
640
641 for (i = 0x80000000; i <= limit; i++) {
642 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
643 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
644 abort();
645 }
646 c = &cpuid_data.entries[cpuid_i++];
647
648 c->function = i;
649 c->flags = 0;
650 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
651 }
652
653 /* Call Centaur's CPUID instructions they are supported. */
654 if (env->cpuid_xlevel2 > 0) {
655 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
656
657 for (i = 0xC0000000; i <= limit; i++) {
658 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
659 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
660 abort();
661 }
662 c = &cpuid_data.entries[cpuid_i++];
663
664 c->function = i;
665 c->flags = 0;
666 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
667 }
668 }
669
670 cpuid_data.cpuid.nent = cpuid_i;
671
672 if (((env->cpuid_version >> 8)&0xF) >= 6
673 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
674 (CPUID_MCE | CPUID_MCA)
675 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
676 uint64_t mcg_cap;
677 int banks;
678 int ret;
679
680 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
681 if (ret < 0) {
682 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
683 return ret;
684 }
685
686 if (banks > MCE_BANKS_DEF) {
687 banks = MCE_BANKS_DEF;
688 }
689 mcg_cap &= MCE_CAP_DEF;
690 mcg_cap |= banks;
691 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
692 if (ret < 0) {
693 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
694 return ret;
695 }
696
697 env->mcg_cap = mcg_cap;
698 }
699
700 qemu_add_vm_change_state_handler(cpu_update_state, env);
701
702 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
703 if (c) {
704 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
705 !!(c->ecx & CPUID_EXT_SMX);
706 }
707
708 cpuid_data.cpuid.padding = 0;
709 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
710 if (r) {
711 return r;
712 }
713
714 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
715 if (r && env->tsc_khz) {
716 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
717 if (r < 0) {
718 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
719 return r;
720 }
721 }
722
723 if (kvm_has_xsave()) {
724 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
725 }
726
727 return 0;
728 }
729
730 void kvm_arch_reset_vcpu(X86CPU *cpu)
731 {
732 CPUX86State *env = &cpu->env;
733
734 env->exception_injected = -1;
735 env->interrupt_injected = -1;
736 env->xcr0 = 1;
737 if (kvm_irqchip_in_kernel()) {
738 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
739 KVM_MP_STATE_UNINITIALIZED;
740 } else {
741 env->mp_state = KVM_MP_STATE_RUNNABLE;
742 }
743 }
744
745 void kvm_arch_do_init_vcpu(X86CPU *cpu)
746 {
747 CPUX86State *env = &cpu->env;
748
749 /* APs get directly into wait-for-SIPI state. */
750 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
751 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
752 }
753 }
754
755 static int kvm_get_supported_msrs(KVMState *s)
756 {
757 static int kvm_supported_msrs;
758 int ret = 0;
759
760 /* first time */
761 if (kvm_supported_msrs == 0) {
762 struct kvm_msr_list msr_list, *kvm_msr_list;
763
764 kvm_supported_msrs = -1;
765
766 /* Obtain MSR list from KVM. These are the MSRs that we must
767 * save/restore */
768 msr_list.nmsrs = 0;
769 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
770 if (ret < 0 && ret != -E2BIG) {
771 return ret;
772 }
773 /* Old kernel modules had a bug and could write beyond the provided
774 memory. Allocate at least a safe amount of 1K. */
775 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
776 msr_list.nmsrs *
777 sizeof(msr_list.indices[0])));
778
779 kvm_msr_list->nmsrs = msr_list.nmsrs;
780 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
781 if (ret >= 0) {
782 int i;
783
784 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
785 if (kvm_msr_list->indices[i] == MSR_STAR) {
786 has_msr_star = true;
787 continue;
788 }
789 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
790 has_msr_hsave_pa = true;
791 continue;
792 }
793 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
794 has_msr_tsc_adjust = true;
795 continue;
796 }
797 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
798 has_msr_tsc_deadline = true;
799 continue;
800 }
801 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
802 has_msr_misc_enable = true;
803 continue;
804 }
805 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
806 has_msr_bndcfgs = true;
807 continue;
808 }
809 }
810 }
811
812 g_free(kvm_msr_list);
813 }
814
815 return ret;
816 }
817
818 int kvm_arch_init(KVMState *s)
819 {
820 uint64_t identity_base = 0xfffbc000;
821 uint64_t shadow_mem;
822 int ret;
823 struct utsname utsname;
824
825 ret = kvm_get_supported_msrs(s);
826 if (ret < 0) {
827 return ret;
828 }
829
830 uname(&utsname);
831 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
832
833 /*
834 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
835 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
836 * Since these must be part of guest physical memory, we need to allocate
837 * them, both by setting their start addresses in the kernel and by
838 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
839 *
840 * Older KVM versions may not support setting the identity map base. In
841 * that case we need to stick with the default, i.e. a 256K maximum BIOS
842 * size.
843 */
844 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
845 /* Allows up to 16M BIOSes. */
846 identity_base = 0xfeffc000;
847
848 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
849 if (ret < 0) {
850 return ret;
851 }
852 }
853
854 /* Set TSS base one page after EPT identity map. */
855 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
856 if (ret < 0) {
857 return ret;
858 }
859
860 /* Tell fw_cfg to notify the BIOS to reserve the range. */
861 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
862 if (ret < 0) {
863 fprintf(stderr, "e820_add_entry() table is full\n");
864 return ret;
865 }
866 qemu_register_reset(kvm_unpoison_all, NULL);
867
868 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
869 "kvm_shadow_mem", -1);
870 if (shadow_mem != -1) {
871 shadow_mem /= 4096;
872 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
873 if (ret < 0) {
874 return ret;
875 }
876 }
877 return 0;
878 }
879
880 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
881 {
882 lhs->selector = rhs->selector;
883 lhs->base = rhs->base;
884 lhs->limit = rhs->limit;
885 lhs->type = 3;
886 lhs->present = 1;
887 lhs->dpl = 3;
888 lhs->db = 0;
889 lhs->s = 1;
890 lhs->l = 0;
891 lhs->g = 0;
892 lhs->avl = 0;
893 lhs->unusable = 0;
894 }
895
896 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
897 {
898 unsigned flags = rhs->flags;
899 lhs->selector = rhs->selector;
900 lhs->base = rhs->base;
901 lhs->limit = rhs->limit;
902 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
903 lhs->present = (flags & DESC_P_MASK) != 0;
904 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
905 lhs->db = (flags >> DESC_B_SHIFT) & 1;
906 lhs->s = (flags & DESC_S_MASK) != 0;
907 lhs->l = (flags >> DESC_L_SHIFT) & 1;
908 lhs->g = (flags & DESC_G_MASK) != 0;
909 lhs->avl = (flags & DESC_AVL_MASK) != 0;
910 lhs->unusable = 0;
911 lhs->padding = 0;
912 }
913
914 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
915 {
916 lhs->selector = rhs->selector;
917 lhs->base = rhs->base;
918 lhs->limit = rhs->limit;
919 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
920 (rhs->present * DESC_P_MASK) |
921 (rhs->dpl << DESC_DPL_SHIFT) |
922 (rhs->db << DESC_B_SHIFT) |
923 (rhs->s * DESC_S_MASK) |
924 (rhs->l << DESC_L_SHIFT) |
925 (rhs->g * DESC_G_MASK) |
926 (rhs->avl * DESC_AVL_MASK);
927 }
928
929 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
930 {
931 if (set) {
932 *kvm_reg = *qemu_reg;
933 } else {
934 *qemu_reg = *kvm_reg;
935 }
936 }
937
938 static int kvm_getput_regs(X86CPU *cpu, int set)
939 {
940 CPUX86State *env = &cpu->env;
941 struct kvm_regs regs;
942 int ret = 0;
943
944 if (!set) {
945 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
946 if (ret < 0) {
947 return ret;
948 }
949 }
950
951 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
952 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
953 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
954 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
955 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
956 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
957 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
958 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
959 #ifdef TARGET_X86_64
960 kvm_getput_reg(&regs.r8, &env->regs[8], set);
961 kvm_getput_reg(&regs.r9, &env->regs[9], set);
962 kvm_getput_reg(&regs.r10, &env->regs[10], set);
963 kvm_getput_reg(&regs.r11, &env->regs[11], set);
964 kvm_getput_reg(&regs.r12, &env->regs[12], set);
965 kvm_getput_reg(&regs.r13, &env->regs[13], set);
966 kvm_getput_reg(&regs.r14, &env->regs[14], set);
967 kvm_getput_reg(&regs.r15, &env->regs[15], set);
968 #endif
969
970 kvm_getput_reg(&regs.rflags, &env->eflags, set);
971 kvm_getput_reg(&regs.rip, &env->eip, set);
972
973 if (set) {
974 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
975 }
976
977 return ret;
978 }
979
980 static int kvm_put_fpu(X86CPU *cpu)
981 {
982 CPUX86State *env = &cpu->env;
983 struct kvm_fpu fpu;
984 int i;
985
986 memset(&fpu, 0, sizeof fpu);
987 fpu.fsw = env->fpus & ~(7 << 11);
988 fpu.fsw |= (env->fpstt & 7) << 11;
989 fpu.fcw = env->fpuc;
990 fpu.last_opcode = env->fpop;
991 fpu.last_ip = env->fpip;
992 fpu.last_dp = env->fpdp;
993 for (i = 0; i < 8; ++i) {
994 fpu.ftwx |= (!env->fptags[i]) << i;
995 }
996 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
997 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
998 fpu.mxcsr = env->mxcsr;
999
1000 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1001 }
1002
1003 #define XSAVE_FCW_FSW 0
1004 #define XSAVE_FTW_FOP 1
1005 #define XSAVE_CWD_RIP 2
1006 #define XSAVE_CWD_RDP 4
1007 #define XSAVE_MXCSR 6
1008 #define XSAVE_ST_SPACE 8
1009 #define XSAVE_XMM_SPACE 40
1010 #define XSAVE_XSTATE_BV 128
1011 #define XSAVE_YMMH_SPACE 144
1012 #define XSAVE_BNDREGS 240
1013 #define XSAVE_BNDCSR 256
1014
1015 static int kvm_put_xsave(X86CPU *cpu)
1016 {
1017 CPUX86State *env = &cpu->env;
1018 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1019 uint16_t cwd, swd, twd;
1020 int i, r;
1021
1022 if (!kvm_has_xsave()) {
1023 return kvm_put_fpu(cpu);
1024 }
1025
1026 memset(xsave, 0, sizeof(struct kvm_xsave));
1027 twd = 0;
1028 swd = env->fpus & ~(7 << 11);
1029 swd |= (env->fpstt & 7) << 11;
1030 cwd = env->fpuc;
1031 for (i = 0; i < 8; ++i) {
1032 twd |= (!env->fptags[i]) << i;
1033 }
1034 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1035 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1036 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1037 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1038 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1039 sizeof env->fpregs);
1040 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1041 sizeof env->xmm_regs);
1042 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1043 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1044 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1045 sizeof env->ymmh_regs);
1046 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1047 sizeof env->bnd_regs);
1048 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1049 sizeof(env->bndcs_regs));
1050 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1051 return r;
1052 }
1053
1054 static int kvm_put_xcrs(X86CPU *cpu)
1055 {
1056 CPUX86State *env = &cpu->env;
1057 struct kvm_xcrs xcrs;
1058
1059 if (!kvm_has_xcrs()) {
1060 return 0;
1061 }
1062
1063 xcrs.nr_xcrs = 1;
1064 xcrs.flags = 0;
1065 xcrs.xcrs[0].xcr = 0;
1066 xcrs.xcrs[0].value = env->xcr0;
1067 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1068 }
1069
1070 static int kvm_put_sregs(X86CPU *cpu)
1071 {
1072 CPUX86State *env = &cpu->env;
1073 struct kvm_sregs sregs;
1074
1075 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1076 if (env->interrupt_injected >= 0) {
1077 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1078 (uint64_t)1 << (env->interrupt_injected % 64);
1079 }
1080
1081 if ((env->eflags & VM_MASK)) {
1082 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1083 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1084 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1085 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1086 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1087 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1088 } else {
1089 set_seg(&sregs.cs, &env->segs[R_CS]);
1090 set_seg(&sregs.ds, &env->segs[R_DS]);
1091 set_seg(&sregs.es, &env->segs[R_ES]);
1092 set_seg(&sregs.fs, &env->segs[R_FS]);
1093 set_seg(&sregs.gs, &env->segs[R_GS]);
1094 set_seg(&sregs.ss, &env->segs[R_SS]);
1095 }
1096
1097 set_seg(&sregs.tr, &env->tr);
1098 set_seg(&sregs.ldt, &env->ldt);
1099
1100 sregs.idt.limit = env->idt.limit;
1101 sregs.idt.base = env->idt.base;
1102 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1103 sregs.gdt.limit = env->gdt.limit;
1104 sregs.gdt.base = env->gdt.base;
1105 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1106
1107 sregs.cr0 = env->cr[0];
1108 sregs.cr2 = env->cr[2];
1109 sregs.cr3 = env->cr[3];
1110 sregs.cr4 = env->cr[4];
1111
1112 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1113 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1114
1115 sregs.efer = env->efer;
1116
1117 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1118 }
1119
1120 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1121 uint32_t index, uint64_t value)
1122 {
1123 entry->index = index;
1124 entry->data = value;
1125 }
1126
1127 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1128 {
1129 CPUX86State *env = &cpu->env;
1130 struct {
1131 struct kvm_msrs info;
1132 struct kvm_msr_entry entries[1];
1133 } msr_data;
1134 struct kvm_msr_entry *msrs = msr_data.entries;
1135
1136 if (!has_msr_tsc_deadline) {
1137 return 0;
1138 }
1139
1140 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1141
1142 msr_data.info.nmsrs = 1;
1143
1144 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1145 }
1146
1147 /*
1148 * Provide a separate write service for the feature control MSR in order to
1149 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1150 * before writing any other state because forcibly leaving nested mode
1151 * invalidates the VCPU state.
1152 */
1153 static int kvm_put_msr_feature_control(X86CPU *cpu)
1154 {
1155 struct {
1156 struct kvm_msrs info;
1157 struct kvm_msr_entry entry;
1158 } msr_data;
1159
1160 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1161 cpu->env.msr_ia32_feature_control);
1162 msr_data.info.nmsrs = 1;
1163 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1164 }
1165
1166 static int kvm_put_msrs(X86CPU *cpu, int level)
1167 {
1168 CPUX86State *env = &cpu->env;
1169 struct {
1170 struct kvm_msrs info;
1171 struct kvm_msr_entry entries[100];
1172 } msr_data;
1173 struct kvm_msr_entry *msrs = msr_data.entries;
1174 int n = 0, i;
1175
1176 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1177 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1178 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1179 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1180 if (has_msr_star) {
1181 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1182 }
1183 if (has_msr_hsave_pa) {
1184 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1185 }
1186 if (has_msr_tsc_adjust) {
1187 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1188 }
1189 if (has_msr_misc_enable) {
1190 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1191 env->msr_ia32_misc_enable);
1192 }
1193 if (has_msr_bndcfgs) {
1194 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1195 }
1196 #ifdef TARGET_X86_64
1197 if (lm_capable_kernel) {
1198 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1199 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1200 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1201 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1202 }
1203 #endif
1204 /*
1205 * The following MSRs have side effects on the guest or are too heavy
1206 * for normal writeback. Limit them to reset or full state updates.
1207 */
1208 if (level >= KVM_PUT_RESET_STATE) {
1209 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1210 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1211 env->system_time_msr);
1212 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1213 if (has_msr_async_pf_en) {
1214 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1215 env->async_pf_en_msr);
1216 }
1217 if (has_msr_pv_eoi_en) {
1218 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1219 env->pv_eoi_en_msr);
1220 }
1221 if (has_msr_kvm_steal_time) {
1222 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1223 env->steal_time_msr);
1224 }
1225 if (has_msr_architectural_pmu) {
1226 /* Stop the counter. */
1227 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1228 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1229
1230 /* Set the counter values. */
1231 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1232 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1233 env->msr_fixed_counters[i]);
1234 }
1235 for (i = 0; i < num_architectural_pmu_counters; i++) {
1236 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1237 env->msr_gp_counters[i]);
1238 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1239 env->msr_gp_evtsel[i]);
1240 }
1241 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1242 env->msr_global_status);
1243 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1244 env->msr_global_ovf_ctrl);
1245
1246 /* Now start the PMU. */
1247 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1248 env->msr_fixed_ctr_ctrl);
1249 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1250 env->msr_global_ctrl);
1251 }
1252 if (has_msr_hv_hypercall) {
1253 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1254 env->msr_hv_guest_os_id);
1255 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1256 env->msr_hv_hypercall);
1257 }
1258 if (has_msr_hv_vapic) {
1259 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1260 env->msr_hv_vapic);
1261 }
1262 if (has_msr_hv_tsc) {
1263 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1264 env->msr_hv_tsc);
1265 }
1266
1267 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1268 * kvm_put_msr_feature_control. */
1269 }
1270 if (env->mcg_cap) {
1271 int i;
1272
1273 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1274 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1275 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1276 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1277 }
1278 }
1279
1280 msr_data.info.nmsrs = n;
1281
1282 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1283
1284 }
1285
1286
1287 static int kvm_get_fpu(X86CPU *cpu)
1288 {
1289 CPUX86State *env = &cpu->env;
1290 struct kvm_fpu fpu;
1291 int i, ret;
1292
1293 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1294 if (ret < 0) {
1295 return ret;
1296 }
1297
1298 env->fpstt = (fpu.fsw >> 11) & 7;
1299 env->fpus = fpu.fsw;
1300 env->fpuc = fpu.fcw;
1301 env->fpop = fpu.last_opcode;
1302 env->fpip = fpu.last_ip;
1303 env->fpdp = fpu.last_dp;
1304 for (i = 0; i < 8; ++i) {
1305 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1306 }
1307 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1308 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1309 env->mxcsr = fpu.mxcsr;
1310
1311 return 0;
1312 }
1313
1314 static int kvm_get_xsave(X86CPU *cpu)
1315 {
1316 CPUX86State *env = &cpu->env;
1317 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1318 int ret, i;
1319 uint16_t cwd, swd, twd;
1320
1321 if (!kvm_has_xsave()) {
1322 return kvm_get_fpu(cpu);
1323 }
1324
1325 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1326 if (ret < 0) {
1327 return ret;
1328 }
1329
1330 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1331 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1332 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1333 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1334 env->fpstt = (swd >> 11) & 7;
1335 env->fpus = swd;
1336 env->fpuc = cwd;
1337 for (i = 0; i < 8; ++i) {
1338 env->fptags[i] = !((twd >> i) & 1);
1339 }
1340 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1341 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1342 env->mxcsr = xsave->region[XSAVE_MXCSR];
1343 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1344 sizeof env->fpregs);
1345 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1346 sizeof env->xmm_regs);
1347 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1348 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1349 sizeof env->ymmh_regs);
1350 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1351 sizeof env->bnd_regs);
1352 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1353 sizeof(env->bndcs_regs));
1354 return 0;
1355 }
1356
1357 static int kvm_get_xcrs(X86CPU *cpu)
1358 {
1359 CPUX86State *env = &cpu->env;
1360 int i, ret;
1361 struct kvm_xcrs xcrs;
1362
1363 if (!kvm_has_xcrs()) {
1364 return 0;
1365 }
1366
1367 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1368 if (ret < 0) {
1369 return ret;
1370 }
1371
1372 for (i = 0; i < xcrs.nr_xcrs; i++) {
1373 /* Only support xcr0 now */
1374 if (xcrs.xcrs[i].xcr == 0) {
1375 env->xcr0 = xcrs.xcrs[i].value;
1376 break;
1377 }
1378 }
1379 return 0;
1380 }
1381
1382 static int kvm_get_sregs(X86CPU *cpu)
1383 {
1384 CPUX86State *env = &cpu->env;
1385 struct kvm_sregs sregs;
1386 uint32_t hflags;
1387 int bit, i, ret;
1388
1389 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1390 if (ret < 0) {
1391 return ret;
1392 }
1393
1394 /* There can only be one pending IRQ set in the bitmap at a time, so try
1395 to find it and save its number instead (-1 for none). */
1396 env->interrupt_injected = -1;
1397 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1398 if (sregs.interrupt_bitmap[i]) {
1399 bit = ctz64(sregs.interrupt_bitmap[i]);
1400 env->interrupt_injected = i * 64 + bit;
1401 break;
1402 }
1403 }
1404
1405 get_seg(&env->segs[R_CS], &sregs.cs);
1406 get_seg(&env->segs[R_DS], &sregs.ds);
1407 get_seg(&env->segs[R_ES], &sregs.es);
1408 get_seg(&env->segs[R_FS], &sregs.fs);
1409 get_seg(&env->segs[R_GS], &sregs.gs);
1410 get_seg(&env->segs[R_SS], &sregs.ss);
1411
1412 get_seg(&env->tr, &sregs.tr);
1413 get_seg(&env->ldt, &sregs.ldt);
1414
1415 env->idt.limit = sregs.idt.limit;
1416 env->idt.base = sregs.idt.base;
1417 env->gdt.limit = sregs.gdt.limit;
1418 env->gdt.base = sregs.gdt.base;
1419
1420 env->cr[0] = sregs.cr0;
1421 env->cr[2] = sregs.cr2;
1422 env->cr[3] = sregs.cr3;
1423 env->cr[4] = sregs.cr4;
1424
1425 env->efer = sregs.efer;
1426
1427 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1428
1429 #define HFLAG_COPY_MASK \
1430 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1431 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1432 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1433 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1434
1435 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1436 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1437 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1438 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1439 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1440 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1441 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1442
1443 if (env->efer & MSR_EFER_LMA) {
1444 hflags |= HF_LMA_MASK;
1445 }
1446
1447 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1448 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1449 } else {
1450 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1451 (DESC_B_SHIFT - HF_CS32_SHIFT);
1452 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1453 (DESC_B_SHIFT - HF_SS32_SHIFT);
1454 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1455 !(hflags & HF_CS32_MASK)) {
1456 hflags |= HF_ADDSEG_MASK;
1457 } else {
1458 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1459 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1460 }
1461 }
1462 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1463
1464 return 0;
1465 }
1466
1467 static int kvm_get_msrs(X86CPU *cpu)
1468 {
1469 CPUX86State *env = &cpu->env;
1470 struct {
1471 struct kvm_msrs info;
1472 struct kvm_msr_entry entries[100];
1473 } msr_data;
1474 struct kvm_msr_entry *msrs = msr_data.entries;
1475 int ret, i, n;
1476
1477 n = 0;
1478 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1479 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1480 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1481 msrs[n++].index = MSR_PAT;
1482 if (has_msr_star) {
1483 msrs[n++].index = MSR_STAR;
1484 }
1485 if (has_msr_hsave_pa) {
1486 msrs[n++].index = MSR_VM_HSAVE_PA;
1487 }
1488 if (has_msr_tsc_adjust) {
1489 msrs[n++].index = MSR_TSC_ADJUST;
1490 }
1491 if (has_msr_tsc_deadline) {
1492 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1493 }
1494 if (has_msr_misc_enable) {
1495 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1496 }
1497 if (has_msr_feature_control) {
1498 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1499 }
1500 if (has_msr_bndcfgs) {
1501 msrs[n++].index = MSR_IA32_BNDCFGS;
1502 }
1503
1504 if (!env->tsc_valid) {
1505 msrs[n++].index = MSR_IA32_TSC;
1506 env->tsc_valid = !runstate_is_running();
1507 }
1508
1509 #ifdef TARGET_X86_64
1510 if (lm_capable_kernel) {
1511 msrs[n++].index = MSR_CSTAR;
1512 msrs[n++].index = MSR_KERNELGSBASE;
1513 msrs[n++].index = MSR_FMASK;
1514 msrs[n++].index = MSR_LSTAR;
1515 }
1516 #endif
1517 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1518 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1519 if (has_msr_async_pf_en) {
1520 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1521 }
1522 if (has_msr_pv_eoi_en) {
1523 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1524 }
1525 if (has_msr_kvm_steal_time) {
1526 msrs[n++].index = MSR_KVM_STEAL_TIME;
1527 }
1528 if (has_msr_architectural_pmu) {
1529 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1530 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1531 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1532 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1533 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1534 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1535 }
1536 for (i = 0; i < num_architectural_pmu_counters; i++) {
1537 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1538 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1539 }
1540 }
1541
1542 if (env->mcg_cap) {
1543 msrs[n++].index = MSR_MCG_STATUS;
1544 msrs[n++].index = MSR_MCG_CTL;
1545 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1546 msrs[n++].index = MSR_MC0_CTL + i;
1547 }
1548 }
1549
1550 if (has_msr_hv_hypercall) {
1551 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1552 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1553 }
1554 if (has_msr_hv_vapic) {
1555 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1556 }
1557 if (has_msr_hv_tsc) {
1558 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1559 }
1560
1561 msr_data.info.nmsrs = n;
1562 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1563 if (ret < 0) {
1564 return ret;
1565 }
1566
1567 for (i = 0; i < ret; i++) {
1568 uint32_t index = msrs[i].index;
1569 switch (index) {
1570 case MSR_IA32_SYSENTER_CS:
1571 env->sysenter_cs = msrs[i].data;
1572 break;
1573 case MSR_IA32_SYSENTER_ESP:
1574 env->sysenter_esp = msrs[i].data;
1575 break;
1576 case MSR_IA32_SYSENTER_EIP:
1577 env->sysenter_eip = msrs[i].data;
1578 break;
1579 case MSR_PAT:
1580 env->pat = msrs[i].data;
1581 break;
1582 case MSR_STAR:
1583 env->star = msrs[i].data;
1584 break;
1585 #ifdef TARGET_X86_64
1586 case MSR_CSTAR:
1587 env->cstar = msrs[i].data;
1588 break;
1589 case MSR_KERNELGSBASE:
1590 env->kernelgsbase = msrs[i].data;
1591 break;
1592 case MSR_FMASK:
1593 env->fmask = msrs[i].data;
1594 break;
1595 case MSR_LSTAR:
1596 env->lstar = msrs[i].data;
1597 break;
1598 #endif
1599 case MSR_IA32_TSC:
1600 env->tsc = msrs[i].data;
1601 break;
1602 case MSR_TSC_ADJUST:
1603 env->tsc_adjust = msrs[i].data;
1604 break;
1605 case MSR_IA32_TSCDEADLINE:
1606 env->tsc_deadline = msrs[i].data;
1607 break;
1608 case MSR_VM_HSAVE_PA:
1609 env->vm_hsave = msrs[i].data;
1610 break;
1611 case MSR_KVM_SYSTEM_TIME:
1612 env->system_time_msr = msrs[i].data;
1613 break;
1614 case MSR_KVM_WALL_CLOCK:
1615 env->wall_clock_msr = msrs[i].data;
1616 break;
1617 case MSR_MCG_STATUS:
1618 env->mcg_status = msrs[i].data;
1619 break;
1620 case MSR_MCG_CTL:
1621 env->mcg_ctl = msrs[i].data;
1622 break;
1623 case MSR_IA32_MISC_ENABLE:
1624 env->msr_ia32_misc_enable = msrs[i].data;
1625 break;
1626 case MSR_IA32_FEATURE_CONTROL:
1627 env->msr_ia32_feature_control = msrs[i].data;
1628 break;
1629 case MSR_IA32_BNDCFGS:
1630 env->msr_bndcfgs = msrs[i].data;
1631 break;
1632 default:
1633 if (msrs[i].index >= MSR_MC0_CTL &&
1634 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1635 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1636 }
1637 break;
1638 case MSR_KVM_ASYNC_PF_EN:
1639 env->async_pf_en_msr = msrs[i].data;
1640 break;
1641 case MSR_KVM_PV_EOI_EN:
1642 env->pv_eoi_en_msr = msrs[i].data;
1643 break;
1644 case MSR_KVM_STEAL_TIME:
1645 env->steal_time_msr = msrs[i].data;
1646 break;
1647 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1648 env->msr_fixed_ctr_ctrl = msrs[i].data;
1649 break;
1650 case MSR_CORE_PERF_GLOBAL_CTRL:
1651 env->msr_global_ctrl = msrs[i].data;
1652 break;
1653 case MSR_CORE_PERF_GLOBAL_STATUS:
1654 env->msr_global_status = msrs[i].data;
1655 break;
1656 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1657 env->msr_global_ovf_ctrl = msrs[i].data;
1658 break;
1659 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1660 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1661 break;
1662 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1663 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1664 break;
1665 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1666 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1667 break;
1668 case HV_X64_MSR_HYPERCALL:
1669 env->msr_hv_hypercall = msrs[i].data;
1670 break;
1671 case HV_X64_MSR_GUEST_OS_ID:
1672 env->msr_hv_guest_os_id = msrs[i].data;
1673 break;
1674 case HV_X64_MSR_APIC_ASSIST_PAGE:
1675 env->msr_hv_vapic = msrs[i].data;
1676 break;
1677 case HV_X64_MSR_REFERENCE_TSC:
1678 env->msr_hv_tsc = msrs[i].data;
1679 break;
1680 }
1681 }
1682
1683 return 0;
1684 }
1685
1686 static int kvm_put_mp_state(X86CPU *cpu)
1687 {
1688 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1689
1690 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1691 }
1692
1693 static int kvm_get_mp_state(X86CPU *cpu)
1694 {
1695 CPUState *cs = CPU(cpu);
1696 CPUX86State *env = &cpu->env;
1697 struct kvm_mp_state mp_state;
1698 int ret;
1699
1700 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1701 if (ret < 0) {
1702 return ret;
1703 }
1704 env->mp_state = mp_state.mp_state;
1705 if (kvm_irqchip_in_kernel()) {
1706 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1707 }
1708 return 0;
1709 }
1710
1711 static int kvm_get_apic(X86CPU *cpu)
1712 {
1713 DeviceState *apic = cpu->apic_state;
1714 struct kvm_lapic_state kapic;
1715 int ret;
1716
1717 if (apic && kvm_irqchip_in_kernel()) {
1718 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1719 if (ret < 0) {
1720 return ret;
1721 }
1722
1723 kvm_get_apic_state(apic, &kapic);
1724 }
1725 return 0;
1726 }
1727
1728 static int kvm_put_apic(X86CPU *cpu)
1729 {
1730 DeviceState *apic = cpu->apic_state;
1731 struct kvm_lapic_state kapic;
1732
1733 if (apic && kvm_irqchip_in_kernel()) {
1734 kvm_put_apic_state(apic, &kapic);
1735
1736 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1737 }
1738 return 0;
1739 }
1740
1741 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1742 {
1743 CPUX86State *env = &cpu->env;
1744 struct kvm_vcpu_events events;
1745
1746 if (!kvm_has_vcpu_events()) {
1747 return 0;
1748 }
1749
1750 events.exception.injected = (env->exception_injected >= 0);
1751 events.exception.nr = env->exception_injected;
1752 events.exception.has_error_code = env->has_error_code;
1753 events.exception.error_code = env->error_code;
1754 events.exception.pad = 0;
1755
1756 events.interrupt.injected = (env->interrupt_injected >= 0);
1757 events.interrupt.nr = env->interrupt_injected;
1758 events.interrupt.soft = env->soft_interrupt;
1759
1760 events.nmi.injected = env->nmi_injected;
1761 events.nmi.pending = env->nmi_pending;
1762 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1763 events.nmi.pad = 0;
1764
1765 events.sipi_vector = env->sipi_vector;
1766
1767 events.flags = 0;
1768 if (level >= KVM_PUT_RESET_STATE) {
1769 events.flags |=
1770 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1771 }
1772
1773 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1774 }
1775
1776 static int kvm_get_vcpu_events(X86CPU *cpu)
1777 {
1778 CPUX86State *env = &cpu->env;
1779 struct kvm_vcpu_events events;
1780 int ret;
1781
1782 if (!kvm_has_vcpu_events()) {
1783 return 0;
1784 }
1785
1786 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1787 if (ret < 0) {
1788 return ret;
1789 }
1790 env->exception_injected =
1791 events.exception.injected ? events.exception.nr : -1;
1792 env->has_error_code = events.exception.has_error_code;
1793 env->error_code = events.exception.error_code;
1794
1795 env->interrupt_injected =
1796 events.interrupt.injected ? events.interrupt.nr : -1;
1797 env->soft_interrupt = events.interrupt.soft;
1798
1799 env->nmi_injected = events.nmi.injected;
1800 env->nmi_pending = events.nmi.pending;
1801 if (events.nmi.masked) {
1802 env->hflags2 |= HF2_NMI_MASK;
1803 } else {
1804 env->hflags2 &= ~HF2_NMI_MASK;
1805 }
1806
1807 env->sipi_vector = events.sipi_vector;
1808
1809 return 0;
1810 }
1811
1812 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1813 {
1814 CPUState *cs = CPU(cpu);
1815 CPUX86State *env = &cpu->env;
1816 int ret = 0;
1817 unsigned long reinject_trap = 0;
1818
1819 if (!kvm_has_vcpu_events()) {
1820 if (env->exception_injected == 1) {
1821 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1822 } else if (env->exception_injected == 3) {
1823 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1824 }
1825 env->exception_injected = -1;
1826 }
1827
1828 /*
1829 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1830 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1831 * by updating the debug state once again if single-stepping is on.
1832 * Another reason to call kvm_update_guest_debug here is a pending debug
1833 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1834 * reinject them via SET_GUEST_DEBUG.
1835 */
1836 if (reinject_trap ||
1837 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1838 ret = kvm_update_guest_debug(cs, reinject_trap);
1839 }
1840 return ret;
1841 }
1842
1843 static int kvm_put_debugregs(X86CPU *cpu)
1844 {
1845 CPUX86State *env = &cpu->env;
1846 struct kvm_debugregs dbgregs;
1847 int i;
1848
1849 if (!kvm_has_debugregs()) {
1850 return 0;
1851 }
1852
1853 for (i = 0; i < 4; i++) {
1854 dbgregs.db[i] = env->dr[i];
1855 }
1856 dbgregs.dr6 = env->dr[6];
1857 dbgregs.dr7 = env->dr[7];
1858 dbgregs.flags = 0;
1859
1860 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1861 }
1862
1863 static int kvm_get_debugregs(X86CPU *cpu)
1864 {
1865 CPUX86State *env = &cpu->env;
1866 struct kvm_debugregs dbgregs;
1867 int i, ret;
1868
1869 if (!kvm_has_debugregs()) {
1870 return 0;
1871 }
1872
1873 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1874 if (ret < 0) {
1875 return ret;
1876 }
1877 for (i = 0; i < 4; i++) {
1878 env->dr[i] = dbgregs.db[i];
1879 }
1880 env->dr[4] = env->dr[6] = dbgregs.dr6;
1881 env->dr[5] = env->dr[7] = dbgregs.dr7;
1882
1883 return 0;
1884 }
1885
1886 int kvm_arch_put_registers(CPUState *cpu, int level)
1887 {
1888 X86CPU *x86_cpu = X86_CPU(cpu);
1889 int ret;
1890
1891 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1892
1893 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
1894 ret = kvm_put_msr_feature_control(x86_cpu);
1895 if (ret < 0) {
1896 return ret;
1897 }
1898 }
1899
1900 ret = kvm_getput_regs(x86_cpu, 1);
1901 if (ret < 0) {
1902 return ret;
1903 }
1904 ret = kvm_put_xsave(x86_cpu);
1905 if (ret < 0) {
1906 return ret;
1907 }
1908 ret = kvm_put_xcrs(x86_cpu);
1909 if (ret < 0) {
1910 return ret;
1911 }
1912 ret = kvm_put_sregs(x86_cpu);
1913 if (ret < 0) {
1914 return ret;
1915 }
1916 /* must be before kvm_put_msrs */
1917 ret = kvm_inject_mce_oldstyle(x86_cpu);
1918 if (ret < 0) {
1919 return ret;
1920 }
1921 ret = kvm_put_msrs(x86_cpu, level);
1922 if (ret < 0) {
1923 return ret;
1924 }
1925 if (level >= KVM_PUT_RESET_STATE) {
1926 ret = kvm_put_mp_state(x86_cpu);
1927 if (ret < 0) {
1928 return ret;
1929 }
1930 ret = kvm_put_apic(x86_cpu);
1931 if (ret < 0) {
1932 return ret;
1933 }
1934 }
1935
1936 ret = kvm_put_tscdeadline_msr(x86_cpu);
1937 if (ret < 0) {
1938 return ret;
1939 }
1940
1941 ret = kvm_put_vcpu_events(x86_cpu, level);
1942 if (ret < 0) {
1943 return ret;
1944 }
1945 ret = kvm_put_debugregs(x86_cpu);
1946 if (ret < 0) {
1947 return ret;
1948 }
1949 /* must be last */
1950 ret = kvm_guest_debug_workarounds(x86_cpu);
1951 if (ret < 0) {
1952 return ret;
1953 }
1954 return 0;
1955 }
1956
1957 int kvm_arch_get_registers(CPUState *cs)
1958 {
1959 X86CPU *cpu = X86_CPU(cs);
1960 int ret;
1961
1962 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1963
1964 ret = kvm_getput_regs(cpu, 0);
1965 if (ret < 0) {
1966 return ret;
1967 }
1968 ret = kvm_get_xsave(cpu);
1969 if (ret < 0) {
1970 return ret;
1971 }
1972 ret = kvm_get_xcrs(cpu);
1973 if (ret < 0) {
1974 return ret;
1975 }
1976 ret = kvm_get_sregs(cpu);
1977 if (ret < 0) {
1978 return ret;
1979 }
1980 ret = kvm_get_msrs(cpu);
1981 if (ret < 0) {
1982 return ret;
1983 }
1984 ret = kvm_get_mp_state(cpu);
1985 if (ret < 0) {
1986 return ret;
1987 }
1988 ret = kvm_get_apic(cpu);
1989 if (ret < 0) {
1990 return ret;
1991 }
1992 ret = kvm_get_vcpu_events(cpu);
1993 if (ret < 0) {
1994 return ret;
1995 }
1996 ret = kvm_get_debugregs(cpu);
1997 if (ret < 0) {
1998 return ret;
1999 }
2000 return 0;
2001 }
2002
2003 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2004 {
2005 X86CPU *x86_cpu = X86_CPU(cpu);
2006 CPUX86State *env = &x86_cpu->env;
2007 int ret;
2008
2009 /* Inject NMI */
2010 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2011 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2012 DPRINTF("injected NMI\n");
2013 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2014 if (ret < 0) {
2015 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2016 strerror(-ret));
2017 }
2018 }
2019
2020 /* Force the VCPU out of its inner loop to process any INIT requests
2021 * or (for userspace APIC, but it is cheap to combine the checks here)
2022 * pending TPR access reports.
2023 */
2024 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2025 cpu->exit_request = 1;
2026 }
2027
2028 if (!kvm_irqchip_in_kernel()) {
2029 /* Try to inject an interrupt if the guest can accept it */
2030 if (run->ready_for_interrupt_injection &&
2031 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2032 (env->eflags & IF_MASK)) {
2033 int irq;
2034
2035 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2036 irq = cpu_get_pic_interrupt(env);
2037 if (irq >= 0) {
2038 struct kvm_interrupt intr;
2039
2040 intr.irq = irq;
2041 DPRINTF("injected interrupt %d\n", irq);
2042 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2043 if (ret < 0) {
2044 fprintf(stderr,
2045 "KVM: injection failed, interrupt lost (%s)\n",
2046 strerror(-ret));
2047 }
2048 }
2049 }
2050
2051 /* If we have an interrupt but the guest is not ready to receive an
2052 * interrupt, request an interrupt window exit. This will
2053 * cause a return to userspace as soon as the guest is ready to
2054 * receive interrupts. */
2055 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2056 run->request_interrupt_window = 1;
2057 } else {
2058 run->request_interrupt_window = 0;
2059 }
2060
2061 DPRINTF("setting tpr\n");
2062 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2063 }
2064 }
2065
2066 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2067 {
2068 X86CPU *x86_cpu = X86_CPU(cpu);
2069 CPUX86State *env = &x86_cpu->env;
2070
2071 if (run->if_flag) {
2072 env->eflags |= IF_MASK;
2073 } else {
2074 env->eflags &= ~IF_MASK;
2075 }
2076 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2077 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2078 }
2079
2080 int kvm_arch_process_async_events(CPUState *cs)
2081 {
2082 X86CPU *cpu = X86_CPU(cs);
2083 CPUX86State *env = &cpu->env;
2084
2085 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2086 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2087 assert(env->mcg_cap);
2088
2089 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2090
2091 kvm_cpu_synchronize_state(cs);
2092
2093 if (env->exception_injected == EXCP08_DBLE) {
2094 /* this means triple fault */
2095 qemu_system_reset_request();
2096 cs->exit_request = 1;
2097 return 0;
2098 }
2099 env->exception_injected = EXCP12_MCHK;
2100 env->has_error_code = 0;
2101
2102 cs->halted = 0;
2103 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2104 env->mp_state = KVM_MP_STATE_RUNNABLE;
2105 }
2106 }
2107
2108 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2109 kvm_cpu_synchronize_state(cs);
2110 do_cpu_init(cpu);
2111 }
2112
2113 if (kvm_irqchip_in_kernel()) {
2114 return 0;
2115 }
2116
2117 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2118 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2119 apic_poll_irq(cpu->apic_state);
2120 }
2121 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2122 (env->eflags & IF_MASK)) ||
2123 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2124 cs->halted = 0;
2125 }
2126 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2127 kvm_cpu_synchronize_state(cs);
2128 do_cpu_sipi(cpu);
2129 }
2130 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2131 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2132 kvm_cpu_synchronize_state(cs);
2133 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2134 env->tpr_access_type);
2135 }
2136
2137 return cs->halted;
2138 }
2139
2140 static int kvm_handle_halt(X86CPU *cpu)
2141 {
2142 CPUState *cs = CPU(cpu);
2143 CPUX86State *env = &cpu->env;
2144
2145 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2146 (env->eflags & IF_MASK)) &&
2147 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2148 cs->halted = 1;
2149 return EXCP_HLT;
2150 }
2151
2152 return 0;
2153 }
2154
2155 static int kvm_handle_tpr_access(X86CPU *cpu)
2156 {
2157 CPUState *cs = CPU(cpu);
2158 struct kvm_run *run = cs->kvm_run;
2159
2160 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2161 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2162 : TPR_ACCESS_READ);
2163 return 1;
2164 }
2165
2166 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2167 {
2168 static const uint8_t int3 = 0xcc;
2169
2170 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2171 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2172 return -EINVAL;
2173 }
2174 return 0;
2175 }
2176
2177 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2178 {
2179 uint8_t int3;
2180
2181 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2182 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2183 return -EINVAL;
2184 }
2185 return 0;
2186 }
2187
2188 static struct {
2189 target_ulong addr;
2190 int len;
2191 int type;
2192 } hw_breakpoint[4];
2193
2194 static int nb_hw_breakpoint;
2195
2196 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2197 {
2198 int n;
2199
2200 for (n = 0; n < nb_hw_breakpoint; n++) {
2201 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2202 (hw_breakpoint[n].len == len || len == -1)) {
2203 return n;
2204 }
2205 }
2206 return -1;
2207 }
2208
2209 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2210 target_ulong len, int type)
2211 {
2212 switch (type) {
2213 case GDB_BREAKPOINT_HW:
2214 len = 1;
2215 break;
2216 case GDB_WATCHPOINT_WRITE:
2217 case GDB_WATCHPOINT_ACCESS:
2218 switch (len) {
2219 case 1:
2220 break;
2221 case 2:
2222 case 4:
2223 case 8:
2224 if (addr & (len - 1)) {
2225 return -EINVAL;
2226 }
2227 break;
2228 default:
2229 return -EINVAL;
2230 }
2231 break;
2232 default:
2233 return -ENOSYS;
2234 }
2235
2236 if (nb_hw_breakpoint == 4) {
2237 return -ENOBUFS;
2238 }
2239 if (find_hw_breakpoint(addr, len, type) >= 0) {
2240 return -EEXIST;
2241 }
2242 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2243 hw_breakpoint[nb_hw_breakpoint].len = len;
2244 hw_breakpoint[nb_hw_breakpoint].type = type;
2245 nb_hw_breakpoint++;
2246
2247 return 0;
2248 }
2249
2250 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2251 target_ulong len, int type)
2252 {
2253 int n;
2254
2255 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2256 if (n < 0) {
2257 return -ENOENT;
2258 }
2259 nb_hw_breakpoint--;
2260 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2261
2262 return 0;
2263 }
2264
2265 void kvm_arch_remove_all_hw_breakpoints(void)
2266 {
2267 nb_hw_breakpoint = 0;
2268 }
2269
2270 static CPUWatchpoint hw_watchpoint;
2271
2272 static int kvm_handle_debug(X86CPU *cpu,
2273 struct kvm_debug_exit_arch *arch_info)
2274 {
2275 CPUState *cs = CPU(cpu);
2276 CPUX86State *env = &cpu->env;
2277 int ret = 0;
2278 int n;
2279
2280 if (arch_info->exception == 1) {
2281 if (arch_info->dr6 & (1 << 14)) {
2282 if (cs->singlestep_enabled) {
2283 ret = EXCP_DEBUG;
2284 }
2285 } else {
2286 for (n = 0; n < 4; n++) {
2287 if (arch_info->dr6 & (1 << n)) {
2288 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2289 case 0x0:
2290 ret = EXCP_DEBUG;
2291 break;
2292 case 0x1:
2293 ret = EXCP_DEBUG;
2294 cs->watchpoint_hit = &hw_watchpoint;
2295 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2296 hw_watchpoint.flags = BP_MEM_WRITE;
2297 break;
2298 case 0x3:
2299 ret = EXCP_DEBUG;
2300 cs->watchpoint_hit = &hw_watchpoint;
2301 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2302 hw_watchpoint.flags = BP_MEM_ACCESS;
2303 break;
2304 }
2305 }
2306 }
2307 }
2308 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2309 ret = EXCP_DEBUG;
2310 }
2311 if (ret == 0) {
2312 cpu_synchronize_state(cs);
2313 assert(env->exception_injected == -1);
2314
2315 /* pass to guest */
2316 env->exception_injected = arch_info->exception;
2317 env->has_error_code = 0;
2318 }
2319
2320 return ret;
2321 }
2322
2323 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2324 {
2325 const uint8_t type_code[] = {
2326 [GDB_BREAKPOINT_HW] = 0x0,
2327 [GDB_WATCHPOINT_WRITE] = 0x1,
2328 [GDB_WATCHPOINT_ACCESS] = 0x3
2329 };
2330 const uint8_t len_code[] = {
2331 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2332 };
2333 int n;
2334
2335 if (kvm_sw_breakpoints_active(cpu)) {
2336 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2337 }
2338 if (nb_hw_breakpoint > 0) {
2339 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2340 dbg->arch.debugreg[7] = 0x0600;
2341 for (n = 0; n < nb_hw_breakpoint; n++) {
2342 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2343 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2344 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2345 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2346 }
2347 }
2348 }
2349
2350 static bool host_supports_vmx(void)
2351 {
2352 uint32_t ecx, unused;
2353
2354 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2355 return ecx & CPUID_EXT_VMX;
2356 }
2357
2358 #define VMX_INVALID_GUEST_STATE 0x80000021
2359
2360 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2361 {
2362 X86CPU *cpu = X86_CPU(cs);
2363 uint64_t code;
2364 int ret;
2365
2366 switch (run->exit_reason) {
2367 case KVM_EXIT_HLT:
2368 DPRINTF("handle_hlt\n");
2369 ret = kvm_handle_halt(cpu);
2370 break;
2371 case KVM_EXIT_SET_TPR:
2372 ret = 0;
2373 break;
2374 case KVM_EXIT_TPR_ACCESS:
2375 ret = kvm_handle_tpr_access(cpu);
2376 break;
2377 case KVM_EXIT_FAIL_ENTRY:
2378 code = run->fail_entry.hardware_entry_failure_reason;
2379 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2380 code);
2381 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2382 fprintf(stderr,
2383 "\nIf you're running a guest on an Intel machine without "
2384 "unrestricted mode\n"
2385 "support, the failure can be most likely due to the guest "
2386 "entering an invalid\n"
2387 "state for Intel VT. For example, the guest maybe running "
2388 "in big real mode\n"
2389 "which is not supported on less recent Intel processors."
2390 "\n\n");
2391 }
2392 ret = -1;
2393 break;
2394 case KVM_EXIT_EXCEPTION:
2395 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2396 run->ex.exception, run->ex.error_code);
2397 ret = -1;
2398 break;
2399 case KVM_EXIT_DEBUG:
2400 DPRINTF("kvm_exit_debug\n");
2401 ret = kvm_handle_debug(cpu, &run->debug.arch);
2402 break;
2403 default:
2404 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2405 ret = -1;
2406 break;
2407 }
2408
2409 return ret;
2410 }
2411
2412 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2413 {
2414 X86CPU *cpu = X86_CPU(cs);
2415 CPUX86State *env = &cpu->env;
2416
2417 kvm_cpu_synchronize_state(cs);
2418 return !(env->cr[0] & CR0_PE_MASK) ||
2419 ((env->segs[R_CS].selector & 3) != 3);
2420 }
2421
2422 void kvm_arch_init_irq_routing(KVMState *s)
2423 {
2424 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2425 /* If kernel can't do irq routing, interrupt source
2426 * override 0->2 cannot be set up as required by HPET.
2427 * So we have to disable it.
2428 */
2429 no_hpet = 1;
2430 }
2431 /* We know at this point that we're using the in-kernel
2432 * irqchip, so we can use irqfds, and on x86 we know
2433 * we can use msi via irqfd and GSI routing.
2434 */
2435 kvm_irqfds_allowed = true;
2436 kvm_msi_via_irqfd_allowed = true;
2437 kvm_gsi_routing_allowed = true;
2438 }
2439
2440 /* Classic KVM device assignment interface. Will remain x86 only. */
2441 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2442 uint32_t flags, uint32_t *dev_id)
2443 {
2444 struct kvm_assigned_pci_dev dev_data = {
2445 .segnr = dev_addr->domain,
2446 .busnr = dev_addr->bus,
2447 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2448 .flags = flags,
2449 };
2450 int ret;
2451
2452 dev_data.assigned_dev_id =
2453 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2454
2455 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2456 if (ret < 0) {
2457 return ret;
2458 }
2459
2460 *dev_id = dev_data.assigned_dev_id;
2461
2462 return 0;
2463 }
2464
2465 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2466 {
2467 struct kvm_assigned_pci_dev dev_data = {
2468 .assigned_dev_id = dev_id,
2469 };
2470
2471 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2472 }
2473
2474 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2475 uint32_t irq_type, uint32_t guest_irq)
2476 {
2477 struct kvm_assigned_irq assigned_irq = {
2478 .assigned_dev_id = dev_id,
2479 .guest_irq = guest_irq,
2480 .flags = irq_type,
2481 };
2482
2483 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2484 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2485 } else {
2486 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2487 }
2488 }
2489
2490 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2491 uint32_t guest_irq)
2492 {
2493 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2494 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2495
2496 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2497 }
2498
2499 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2500 {
2501 struct kvm_assigned_pci_dev dev_data = {
2502 .assigned_dev_id = dev_id,
2503 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2504 };
2505
2506 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2507 }
2508
2509 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2510 uint32_t type)
2511 {
2512 struct kvm_assigned_irq assigned_irq = {
2513 .assigned_dev_id = dev_id,
2514 .flags = type,
2515 };
2516
2517 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2518 }
2519
2520 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2521 {
2522 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2523 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2524 }
2525
2526 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2527 {
2528 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2529 KVM_DEV_IRQ_GUEST_MSI, virq);
2530 }
2531
2532 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2533 {
2534 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2535 KVM_DEV_IRQ_HOST_MSI);
2536 }
2537
2538 bool kvm_device_msix_supported(KVMState *s)
2539 {
2540 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2541 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2542 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2543 }
2544
2545 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2546 uint32_t nr_vectors)
2547 {
2548 struct kvm_assigned_msix_nr msix_nr = {
2549 .assigned_dev_id = dev_id,
2550 .entry_nr = nr_vectors,
2551 };
2552
2553 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2554 }
2555
2556 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2557 int virq)
2558 {
2559 struct kvm_assigned_msix_entry msix_entry = {
2560 .assigned_dev_id = dev_id,
2561 .gsi = virq,
2562 .entry = vector,
2563 };
2564
2565 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2566 }
2567
2568 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2569 {
2570 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2571 KVM_DEV_IRQ_GUEST_MSIX, 0);
2572 }
2573
2574 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2575 {
2576 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2577 KVM_DEV_IRQ_HOST_MSIX);
2578 }
CRIS target port of Qemu