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2023-09-15	LIU Zhiwei	accel/tcg: Fix the comment for CPUTLBEntryFull Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-09-11	LIU Zhiwei	linux-user/riscv: Use abi type for target_ucontext Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-09-11	LIU Zhiwei	target/riscv: Fix zfa fleq.d and fltq.d Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-09-11	LIU Zhiwei	target/riscv: Fix page_check_range use in fault-only... Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-07-10	LIU Zhiwei	target/riscv: Use xl instead of mxl for disassemble Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Add a tb flags field for vstart Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Encode the FS and VS on a normal way... Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Add a general status enum for extensions Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Extract virt enabled state from tb flags Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Convert env->virt to a bool env->virt_enabled Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Fix itrigger when icount is used Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-05-05	LIU Zhiwei	target/riscv: Fix priv version dependency for vector... Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-02-23	LIU Zhiwei	target/riscv: Fix vslide1up.vf and vslide1down.vf Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-01-06	LIU Zhiwei	target/riscv: Add itrigger_enabled field to CPURISCVState Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-01-06	LIU Zhiwei	target/riscv: Enable native debug itrigger Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-01-06	LIU Zhiwei	target/riscv: Add itrigger support when icount is enabled Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-01-06	LIU Zhiwei	target/riscv: Add itrigger support when icount is not... Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2023-01-06	LIU Zhiwei	target/riscv: Fix PMP propagation for tlb Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>	commit \| commitdiff \| tree
2022-02-16	LIU Zhiwei	target/riscv: Fix vill field write in vtype Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Relax UXL field for debugging Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Enable uxl field write Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Set default XLEN for hypervisor Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Adjust scalar reg in vector with XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Adjust vector address with mask Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Fix check range for first fault only Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Remove VILL field in VTYPE Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Adjust vsetvl according to XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Split out the vill from vtype Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Split pm_enabled into mask and base Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Calculate address according to XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Alloc tcg global for cur_pm[mask\|base] Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Create current pm fields in env Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Adjust csr write mask with XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Relax debug check for pm write Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Use gdb xml according to max mxlen Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Extend pc for runtime pc write Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Ignore the pc bits above XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Create xl field in env Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Sign extend pc for different XLEN Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Sign extend link reg for jal and jalr Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Don't save pc when exception return Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2022-01-21	LIU Zhiwei	target/riscv: Adjust pmpcfg access with mxl Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-12-20	LIU Zhiwei	target/riscv: rvv-1.0: add vcsr register Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-12-20	LIU Zhiwei	target/riscv: rvv-1.0: add sstatus VS field Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-12-20	LIU Zhiwei	target/riscv: rvv-1.0: add mstatus VS field Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-09-20	LIU Zhiwei	target/riscv: Fix satp write Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-09-01	LIU Zhiwei	target/riscv: Add User CSRs read-only check Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-09-01	LIU Zhiwei	target/riscv: Don't wrongly override isa version Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-29	LIU Zhiwei	tcg: Implement tcg_gen_vec_add{sub}32_tl Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-29	LIU Zhiwei	tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-29	LIU Zhiwei	tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-29	LIU Zhiwei	tcg: Add tcg_gen_vec_add{sub}8_i32 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-29	LIU Zhiwei	tcg: Add tcg_gen_vec_add{sub}16_i32 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-06-07	LIU Zhiwei	target/riscv: Pass the same value to oprsz and maxsz. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2021-05-11	LIU Zhiwei	target/riscv: Fixup saturate subtract function Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-08-28	LIU Zhiwei	softfloat: Define misc operations for bfloat16 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-08-28	LIU Zhiwei	softfloat: Define convert operations for bfloat16 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-08-28	LIU Zhiwei	softfloat: Define operations for bfloat16 Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-08-22	LIU Zhiwei	target/riscv: check before allocating TCG temps Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-08-22	LIU Zhiwei	target/riscv: Clean up fmv.w.x Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-22	LIU Zhiwei	target/riscv: fix vector index load/store constraints Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-22	LIU Zhiwei	target/riscv: Quiet Coverity complains about vamo* Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-15	LIU Zhiwei	fpu/softfloat: fix up float16 nan recognition Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: configure and turn on vector extension... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector compress instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector register gather instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector slide instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: floating-point scalar move instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: integer scalar move instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: integer extract instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector element index instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector iota instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: set-X-first mask bit Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vmfirst find-first-set mask bit Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector mask population count vmpopc Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector mask-register logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector widening floating-point reduction... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width floating-point reduction... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector wideing integer reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width integer reduction... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: narrowing floating-point/integer type... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: widening floating-point/integer type... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point/integer type-convert... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point merge instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point classify instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point compare instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point sign-injection... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point min/max instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector floating-point square-root instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector widening floating-point fused... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width floating-point fused... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector widening floating-point multiply Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width floating-point multiply... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector widening floating-point add/subtract... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width floating-point add... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector narrowing fixed-point clip instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width scaling shift instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector widening saturating scaled multiply-add Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width fractional multiply... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
2020-07-02	LIU Zhiwei	target/riscv: vector single-width averaging add and... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>	commit \| commitdiff \| tree
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