From 0ed93f4c05896145434adbce5fa328643260dd2e Mon Sep 17 00:00:00 2001 From: Ani Sinha Date: Fri, 18 Sep 2020 14:11:09 +0530 Subject: [PATCH] tests/acpi: update golden master DSDT binary table blobs for q35 In the previously applied commit ("piix4: don't reserve hw resources when hotplug is off globally"), we make changes to the ACPI DSDT tables such that some ACPI code are not generated when bsel is absent. Since as of this point in time, in q35 machines, we do not use bsel for pci buses, we need to update the DSDT table blobs. This patch updates the DSDT golden master tables for q35 machines. At the same time, we clear bios-tables-test-allowed-diff.h for future changes which update tables. Following is a typical diff between the q35 acpi DSDT table blobs: @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180105 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Tue Sep 15 18:52:47 2020 + * Disassembly of /tmp/aml-3O0DR0, Tue Sep 15 18:52:47 2020 * * Original Table Header: * Signature "DSDT" - * Length 0x00001DFE (7678) + * Length 0x00001DF6 (7670) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xAC + * Checksum 0x17 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -3113,24 +3113,20 @@ Name (_ADR, 0x00010000) // _ADR: Address Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State { Return (Zero) } Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State { Return (Zero) } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (Zero) } } - - Method (PCNT, 0, NotSerialized) - { - } } } } Signed-off-by: Ani Sinha Acked-by: Igor Mammedov Message-Id: <20200918084111.15339-12-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. 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$(MAKE) check-unit Run qobject tests" + @echo " $(MAKE) check-speed Run qobject speed tests" + @echo " $(MAKE) check-qapi-schema Run QAPI schema tests" + @echo " $(MAKE) check-block Run block tests" + @echo " $(MAKE) check-tcg Run TCG tests" + @echo " $(MAKE) check-acceptance Run all acceptance (functional) tests" + @echo " $(MAKE) check-report.html Generates an HTML test report" + @echo " $(MAKE) check-venv Creates a Python venv for tests" + @echo " $(MAKE) check-clean Clean the tests" + @echo + @echo "Please note that HTML reports do not regenerate if the unit tests" + @echo "has not changed." + @echo + @echo "The variable SPEED can be set to control the gtester speed setting." + @echo "Default options are -k and (for $(MAKE) V=1) --verbose; they can be" + @echo "changed with variable GTESTER_OPTIONS." + +ifneq ($(wildcard config-host.mak),) +export SRC_PATH + +# TODO don't duplicate $(SRC_PATH)/Makefile's qapi-py here +qapi-py = $(SRC_PATH)/scripts/qapi/commands.py \ +$(SRC_PATH)/scripts/qapi/events.py \ +$(SRC_PATH)/scripts/qapi/introspect.py \ +$(SRC_PATH)/scripts/qapi/types.py \ +$(SRC_PATH)/scripts/qapi/visit.py \ +$(SRC_PATH)/scripts/qapi/common.py \ +$(SRC_PATH)/scripts/qapi/doc.py \ +$(SRC_PATH)/scripts/qapi-gen.py + +# Get the list of all supported sysemu targets +SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \ + $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak))) + +check-unit-y += tests/check-qdict$(EXESUF) +check-unit-y += tests/check-block-qdict$(EXESUF) +check-unit-y += tests/test-char$(EXESUF) +check-unit-y += tests/check-qnum$(EXESUF) +check-unit-y += tests/check-qstring$(EXESUF) +check-unit-y += tests/check-qlist$(EXESUF) +check-unit-y += tests/check-qnull$(EXESUF) +check-unit-y += tests/check-qobject$(EXESUF) +check-unit-y += tests/check-qjson$(EXESUF) +check-unit-y += tests/check-qlit$(EXESUF) +check-unit-y += tests/test-qobject-output-visitor$(EXESUF) +check-unit-y += tests/test-clone-visitor$(EXESUF) +check-unit-y += tests/test-qobject-input-visitor$(EXESUF) +check-unit-y += tests/test-qmp-cmds$(EXESUF) +check-unit-y += tests/test-string-input-visitor$(EXESUF) +check-unit-y += tests/test-string-output-visitor$(EXESUF) +check-unit-y += tests/test-qmp-event$(EXESUF) +check-unit-y += tests/test-opts-visitor$(EXESUF) +check-unit-y += tests/test-coroutine$(EXESUF) +check-unit-y += tests/test-visitor-serialization$(EXESUF) +check-unit-y += tests/test-iov$(EXESUF) +check-unit-y += tests/test-aio$(EXESUF) +check-unit-y += tests/test-aio-multithread$(EXESUF) +check-unit-y += tests/test-throttle$(EXESUF) +check-unit-y += tests/test-thread-pool$(EXESUF) +check-unit-y += tests/test-hbitmap$(EXESUF) +check-unit-y += tests/test-bdrv-drain$(EXESUF) +check-unit-y += tests/test-blockjob$(EXESUF) +check-unit-y += tests/test-blockjob-txn$(EXESUF) +check-unit-y += tests/test-block-backend$(EXESUF) +check-unit-y += tests/test-image-locking$(EXESUF) +check-unit-y += tests/test-x86-cpuid$(EXESUF) +# all code tested by test-x86-cpuid is inside topology.h +ifeq ($(CONFIG_SOFTMMU),y) +check-unit-y += tests/test-xbzrle$(EXESUF) +check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) +endif +check-unit-y += tests/test-cutils$(EXESUF) +check-unit-y += tests/test-shift128$(EXESUF) +check-unit-y += tests/test-mul64$(EXESUF) +check-unit-y += tests/test-int128$(EXESUF) +# all code tested by test-int128 is inside int128.h +check-unit-y += tests/rcutorture$(EXESUF) +check-unit-y += tests/test-rcu-list$(EXESUF) +check-unit-y += tests/test-rcu-simpleq$(EXESUF) +check-unit-y += tests/test-rcu-tailq$(EXESUF) +check-unit-y += tests/test-qdist$(EXESUF) +check-unit-y += tests/test-qht$(EXESUF) +# FIXME: {test-qht-par + gprof} often break on Travis CI +check-unit-$(call lnot,$(CONFIG_GPROF)) += tests/test-qht-par$(EXESUF) +check-unit-y += tests/test-bitops$(EXESUF) +check-unit-y += tests/test-bitcnt$(EXESUF) +check-unit-y += tests/test-qdev-global-props$(EXESUF) +check-unit-y += tests/check-qom-interface$(EXESUF) +check-unit-y += tests/check-qom-proplist$(EXESUF) +check-unit-y += tests/test-qemu-opts$(EXESUF) +check-unit-y += tests/test-keyval$(EXESUF) +check-unit-y += tests/test-write-threshold$(EXESUF) +check-unit-y += tests/test-crypto-hash$(EXESUF) +check-speed-y += tests/benchmark-crypto-hash$(EXESUF) +check-unit-y += tests/test-crypto-hmac$(EXESUF) +check-speed-y += tests/benchmark-crypto-hmac$(EXESUF) +check-unit-y += tests/test-crypto-cipher$(EXESUF) +check-speed-y += tests/benchmark-crypto-cipher$(EXESUF) +check-unit-y += tests/test-crypto-secret$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF) +ifneq (,$(findstring qemu-ga,$(TOOLS))) +check-unit-$(CONFIG_LINUX) += tests/test-qga$(EXESUF) +endif +check-unit-y += tests/test-timed-average$(EXESUF) +check-unit-y += tests/test-util-sockets$(EXESUF) +check-unit-y += tests/test-io-task$(EXESUF) +check-unit-y += tests/test-io-channel-socket$(EXESUF) +check-unit-y += tests/test-io-channel-file$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-io-channel-tls$(EXESUF) +check-unit-y += tests/test-io-channel-command$(EXESUF) +check-unit-y += tests/test-io-channel-buffer$(EXESUF) +check-unit-y += tests/test-base64$(EXESUF) +check-unit-$(if $(CONFIG_NETTLE),y,$(CONFIG_GCRYPT)) += tests/test-crypto-pbkdf$(EXESUF) +check-unit-y += tests/test-crypto-ivgen$(EXESUF) +check-unit-y += tests/test-crypto-afsplit$(EXESUF) +check-unit-y += tests/test-crypto-xts$(EXESUF) +check-unit-y += tests/test-crypto-block$(EXESUF) +check-unit-y += tests/test-logging$(EXESUF) +check-unit-$(CONFIG_REPLICATION) += tests/test-replication$(EXESUF) +check-unit-y += tests/test-bufferiszero$(EXESUF) +check-unit-y += tests/test-uuid$(EXESUF) +check-unit-y += tests/ptimer-test$(EXESUF) +check-unit-y += tests/test-qapi-util$(EXESUF) + +check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh + +# All QTests for now are POSIX-only, but the dependencies are +# really in libqtest, not in the testcases themselves. + +check-qtest-generic-y += tests/qmp-test$(EXESUF) +check-qtest-generic-y += tests/qmp-cmd-test$(EXESUF) + +check-qtest-generic-y += tests/device-introspect-test$(EXESUF) +check-qtest-generic-y += tests/cdrom-test$(EXESUF) + +check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF) + +check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF) + +check-qtest-virtio-y += tests/virtio-net-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_BALLOON) += tests/virtio-balloon-test$(EXESUF) +check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_RNG) += tests/virtio-rng-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_SCSI) += tests/virtio-scsi-test$(EXESUF) +ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy) +check-qtest-virtio-$(CONFIG_VIRTIO_9P) += tests/virtio-9p-test$(EXESUF) +endif +check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF) +check-qtest-virtio-y += $(check-qtest-virtioserial-y) + +check-qtest-pci-y += tests/e1000-test$(EXESUF) +check-qtest-pci-y += tests/e1000e-test$(EXESUF) +check-qtest-pci-$(CONFIG_RTL8139_PCI) += tests/rtl8139-test$(EXESUF) +check-qtest-pci-$(CONFIG_PCNET_PCI) += tests/pcnet-test$(EXESUF) +check-qtest-pci-$(CONFIG_EEPRO100_PCI) += tests/eepro100-test$(EXESUF) +check-qtest-pci-$(CONFIG_NE2000_PCI) += tests/ne2000-test$(EXESUF) +check-qtest-pci-$(CONFIG_NVME_PCI) += tests/nvme-test$(EXESUF) +check-qtest-pci-$(CONFIG_AC97) += tests/ac97-test$(EXESUF) +check-qtest-pci-$(CONFIG_ES1370) += tests/es1370-test$(EXESUF) +check-qtest-pci-y += $(check-qtest-virtio-y) +check-qtest-pci-$(CONFIG_IPACK) += tests/tpci200-test$(EXESUF) +check-qtest-pci-$(CONFIG_IPACK) += $(check-qtest-ipack-y) +check-qtest-pci-y += tests/display-vga-test$(EXESUF) +check-qtest-pci-$(CONFIG_HDA) += tests/intel-hda-test$(EXESUF) +check-qtest-pci-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF) +check-qtest-pci-y += tests/megasas-test$(EXESUF) + +check-qtest-i386-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-i386-y += tests/fdc-test$(EXESUF) +check-qtest-i386-y += tests/ide-test$(EXESUF) +check-qtest-i386-y += tests/ahci-test$(EXESUF) +check-qtest-i386-y += tests/hd-geo-test$(EXESUF) +check-qtest-i386-y += tests/boot-order-test$(EXESUF) +check-qtest-i386-y += tests/bios-tables-test$(EXESUF) +check-qtest-i386-$(CONFIG_SGA) += tests/boot-serial-test$(EXESUF) +check-qtest-i386-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-i386-y += tests/rtc-test$(EXESUF) +check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF) +check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF) +check-qtest-i386-y += tests/i440fx-test$(EXESUF) +check-qtest-i386-y += tests/fw_cfg-test$(EXESUF) +check-qtest-i386-y += tests/drive_del-test$(EXESUF) +check-qtest-i386-$(CONFIG_WDT_IB700) += tests/wdt_ib700-test$(EXESUF) +check-qtest-i386-y += tests/tco-test$(EXESUF) +check-qtest-i386-y += $(check-qtest-pci-y) +check-qtest-i386-$(CONFIG_VMXNET3_PCI) += tests/vmxnet3-test$(EXESUF) +check-qtest-i386-$(CONFIG_PVPANIC) += tests/pvpanic-test$(EXESUF) +check-qtest-i386-$(CONFIG_I82801B11) += tests/i82801b11-test$(EXESUF) +check-qtest-i386-$(CONFIG_IOH3420) += tests/ioh3420-test$(EXESUF) +check-qtest-i386-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF) +check-qtest-i386-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF) +ifeq ($(CONFIG_USB_ECHI)$(CONFIG_USB_UHCI),yy) +check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF) +endif +check-qtest-i386-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF) +check-qtest-i386-y += tests/cpu-plug-test$(EXESUF) +check-qtest-i386-y += tests/q35-test$(EXESUF) +check-qtest-i386-y += tests/vmgenid-test$(EXESUF) +check-qtest-i386-$(CONFIG_VHOST_USER_NET_TEST_i386) += tests/vhost-user-test$(EXESUF) +ifeq ($(CONFIG_VHOST_USER_NET_TEST_i386),) +check-qtest-x86_64-$(CONFIG_VHOST_USER_NET_TEST_x86_64) += tests/vhost-user-test$(EXESUF) +endif +check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-swtpm-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-swtpm-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-test$(EXESUF) +check-qtest-i386-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-i386-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF) +check-qtest-i386-y += tests/migration-test$(EXESUF) +check-qtest-i386-y += tests/test-x86-cpuid-compat$(EXESUF) +check-qtest-i386-y += tests/numa-test$(EXESUF) +check-qtest-x86_64-y += $(check-qtest-i386-y) +check-qtest-x86_64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) + +check-qtest-alpha-y += tests/boot-serial-test$(EXESUF) +check-qtest-alpha-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-hppa-y += tests/boot-serial-test$(EXESUF) +check-qtest-hppa-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-m68k-y = tests/boot-serial-test$(EXESUF) + +check-qtest-microblaze-y += tests/boot-serial-test$(EXESUF) + +check-qtest-mips-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-mips64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips64-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-mips64el-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips64el-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-moxie-y += tests/boot-serial-test$(EXESUF) + +check-qtest-ppc-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-ppc-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc-y += tests/prom-env-test$(EXESUF) +check-qtest-ppc-y += tests/drive_del-test$(EXESUF) +check-qtest-ppc-y += tests/boot-serial-test$(EXESUF) +check-qtest-ppc-y += tests/m48t59-test$(EXESUF) + +check-qtest-ppc64-y += $(check-qtest-ppc-y) +check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF) +check-qtest-ppc64-y += tests/pnv-xscom-test$(EXESUF) +check-qtest-ppc64-y += tests/migration-test$(EXESUF) +check-qtest-ppc64-y += tests/rtas-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF) +check-qtest-ppc64-y += $(check-qtest-virtio-y) +check-qtest-ppc64-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-ppc64-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-ppc64-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF) +check-qtest-ppc64-y += tests/display-vga-test$(EXESUF) +check-qtest-ppc64-y += tests/numa-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF) +check-qtest-ppc64-y += tests/cpu-plug-test$(EXESUF) + +check-qtest-sh4-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) + +check-qtest-sh4eb-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) + +check-qtest-sparc-y += tests/prom-env-test$(EXESUF) +check-qtest-sparc-y += tests/m48t59-test$(EXESUF) +check-qtest-sparc-y += tests/boot-serial-test$(EXESUF) + +check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-sparc64-y += tests/prom-env-test$(EXESUF) +check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF) + +check-qtest-arm-y += tests/tmp105-test$(EXESUF) +check-qtest-arm-y += tests/pca9552-test$(EXESUF) +check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/microbit-test$(EXESUF) +check-qtest-arm-y += tests/m25p80-test$(EXESUF) +check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) +check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF) +check-qtest-arm-y += tests/boot-serial-test$(EXESUF) +check-qtest-arm-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) +check-qtest-arm-y += tests/hexloader-test$(EXESUF) + +check-qtest-aarch64-y = tests/numa-test$(EXESUF) +check-qtest-aarch64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) +check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF) +check-qtest-aarch64-y += tests/migration-test$(EXESUF) + +check-qtest-microblazeel-y += $(check-qtest-microblaze-y) + +check-qtest-xtensaeb-y += $(check-qtest-xtensa-y) + +check-qtest-s390x-y = tests/boot-serial-test$(EXESUF) +check-qtest-s390x-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-s390x-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-redirector$(EXESUF) +check-qtest-s390x-y += tests/drive_del-test$(EXESUF) +check-qtest-s390x-y += tests/virtio-ccw-test$(EXESUF) +check-qtest-s390x-y += tests/cpu-plug-test$(EXESUF) +check-qtest-s390x-y += tests/migration-test$(EXESUF) + +check-qtest-generic-y += tests/machine-none-test$(EXESUF) +check-qtest-generic-y += tests/qom-test$(EXESUF) +check-qtest-generic-y += tests/test-hmp$(EXESUF) + +qapi-schema += alternate-any.json +qapi-schema += alternate-array.json +qapi-schema += alternate-base.json +qapi-schema += alternate-clash.json +qapi-schema += alternate-conflict-dict.json +qapi-schema += alternate-conflict-enum-bool.json +qapi-schema += alternate-conflict-enum-int.json +qapi-schema += alternate-conflict-string.json +qapi-schema += alternate-conflict-bool-string.json +qapi-schema += alternate-conflict-num-string.json +qapi-schema += alternate-empty.json +qapi-schema += alternate-invalid-dict.json +qapi-schema += alternate-nested.json +qapi-schema += alternate-unknown.json +qapi-schema += args-alternate.json +qapi-schema += args-any.json +qapi-schema += args-array-empty.json +qapi-schema += args-array-unknown.json +qapi-schema += args-bad-boxed.json +qapi-schema += args-boxed-anon.json +qapi-schema += args-boxed-empty.json +qapi-schema += args-boxed-string.json +qapi-schema += args-int.json +qapi-schema += args-invalid.json +qapi-schema += args-member-array-bad.json +qapi-schema += args-member-case.json +qapi-schema += args-member-unknown.json +qapi-schema += args-name-clash.json +qapi-schema += args-union.json +qapi-schema += args-unknown.json +qapi-schema += bad-base.json +qapi-schema += bad-data.json +qapi-schema += bad-ident.json +qapi-schema += bad-if.json +qapi-schema += bad-if-empty.json +qapi-schema += bad-if-empty-list.json +qapi-schema += bad-if-list.json +qapi-schema += bad-type-bool.json +qapi-schema += bad-type-dict.json +qapi-schema += bad-type-int.json +qapi-schema += base-cycle-direct.json +qapi-schema += base-cycle-indirect.json +qapi-schema += command-int.json +qapi-schema += comments.json +qapi-schema += doc-bad-alternate-member.json +qapi-schema += doc-bad-command-arg.json +qapi-schema += doc-bad-section.json +qapi-schema += doc-bad-symbol.json +qapi-schema += doc-bad-union-member.json +qapi-schema += doc-before-include.json +qapi-schema += doc-before-pragma.json +qapi-schema += doc-duplicated-arg.json +qapi-schema += doc-duplicated-return.json +qapi-schema += doc-duplicated-since.json +qapi-schema += doc-empty-arg.json +qapi-schema += doc-empty-section.json +qapi-schema += doc-empty-symbol.json +qapi-schema += doc-good.json +qapi-schema += doc-interleaved-section.json +qapi-schema += doc-invalid-end.json +qapi-schema += doc-invalid-end2.json +qapi-schema += doc-invalid-return.json +qapi-schema += doc-invalid-section.json +qapi-schema += doc-invalid-start.json +qapi-schema += doc-missing-colon.json +qapi-schema += doc-missing-expr.json +qapi-schema += doc-missing-space.json +qapi-schema += doc-missing.json +qapi-schema += doc-no-symbol.json +qapi-schema += double-data.json +qapi-schema += double-type.json +qapi-schema += duplicate-key.json +qapi-schema += empty.json +qapi-schema += enum-bad-member.json +qapi-schema += enum-bad-name.json +qapi-schema += enum-bad-prefix.json +qapi-schema += enum-clash-member.json +qapi-schema += enum-dict-member-unknown.json +qapi-schema += enum-if-invalid.json +qapi-schema += enum-int-member.json +qapi-schema += enum-member-case.json +qapi-schema += enum-missing-data.json +qapi-schema += enum-wrong-data.json +qapi-schema += escape-outside-string.json +qapi-schema += escape-too-big.json +qapi-schema += escape-too-short.json +qapi-schema += event-boxed-empty.json +qapi-schema += event-case.json +qapi-schema += event-member-invalid-dict.json +qapi-schema += event-nest-struct.json +qapi-schema += flat-union-array-branch.json +qapi-schema += flat-union-bad-base.json +qapi-schema += flat-union-bad-discriminator.json +qapi-schema += flat-union-base-any.json +qapi-schema += flat-union-base-union.json +qapi-schema += flat-union-clash-member.json +qapi-schema += flat-union-empty.json +qapi-schema += flat-union-inline.json +qapi-schema += flat-union-inline-invalid-dict.json +qapi-schema += flat-union-int-branch.json +qapi-schema += flat-union-invalid-branch-key.json +qapi-schema += flat-union-invalid-discriminator.json +qapi-schema += flat-union-invalid-if-discriminator.json +qapi-schema += flat-union-no-base.json +qapi-schema += flat-union-optional-discriminator.json +qapi-schema += flat-union-string-discriminator.json +qapi-schema += funny-char.json +qapi-schema += ident-with-escape.json +qapi-schema += include-before-err.json +qapi-schema += include-cycle.json +qapi-schema += include-extra-junk.json +qapi-schema += include-format-err.json +qapi-schema += include-nested-err.json +qapi-schema += include-no-file.json +qapi-schema += include-non-file.json +qapi-schema += include-relpath.json +qapi-schema += include-repetition.json +qapi-schema += include-self-cycle.json +qapi-schema += include-simple.json +qapi-schema += indented-expr.json +qapi-schema += leading-comma-list.json +qapi-schema += leading-comma-object.json +qapi-schema += missing-colon.json +qapi-schema += missing-comma-list.json +qapi-schema += missing-comma-object.json +qapi-schema += missing-type.json +qapi-schema += nested-struct-data.json +qapi-schema += nested-struct-data-invalid-dict.json +qapi-schema += non-objects.json +qapi-schema += oob-test.json +qapi-schema += allow-preconfig-test.json +qapi-schema += pragma-doc-required-crap.json +qapi-schema += pragma-extra-junk.json +qapi-schema += pragma-name-case-whitelist-crap.json +qapi-schema += pragma-non-dict.json +qapi-schema += pragma-returns-whitelist-crap.json +qapi-schema += qapi-schema-test.json +qapi-schema += quoted-structural-chars.json +qapi-schema += redefined-builtin.json +qapi-schema += redefined-command.json +qapi-schema += redefined-event.json +qapi-schema += redefined-type.json +qapi-schema += reserved-command-q.json +qapi-schema += reserved-enum-q.json +qapi-schema += reserved-member-has.json +qapi-schema += reserved-member-q.json +qapi-schema += reserved-member-u.json +qapi-schema += reserved-member-underscore.json +qapi-schema += reserved-type-kind.json +qapi-schema += reserved-type-list.json +qapi-schema += returns-alternate.json +qapi-schema += returns-array-bad.json +qapi-schema += returns-dict.json +qapi-schema += returns-unknown.json +qapi-schema += returns-whitelist.json +qapi-schema += struct-base-clash-deep.json +qapi-schema += struct-base-clash.json +qapi-schema += struct-data-invalid.json +qapi-schema += struct-member-invalid-dict.json +qapi-schema += struct-member-invalid.json +qapi-schema += trailing-comma-list.json +qapi-schema += trailing-comma-object.json +qapi-schema += type-bypass-bad-gen.json +qapi-schema += unclosed-list.json +qapi-schema += unclosed-object.json +qapi-schema += unclosed-string.json +qapi-schema += unicode-str.json +qapi-schema += union-base-empty.json +qapi-schema += union-base-no-discriminator.json +qapi-schema += union-branch-case.json +qapi-schema += union-branch-invalid-dict.json +qapi-schema += union-clash-branches.json +qapi-schema += union-empty.json +qapi-schema += union-invalid-base.json +qapi-schema += union-optional-branch.json +qapi-schema += union-unknown.json +qapi-schema += unknown-escape.json +qapi-schema += unknown-expr-key.json + + +check-qapi-schema-y := $(addprefix tests/qapi-schema/, $(qapi-schema)) + +GENERATED_FILES += tests/test-qapi-types.h tests/test-qapi-visit.h \ + tests/test-qapi-commands.h tests/test-qapi-events.h \ + tests/test-qapi-introspect.h + +test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \ + tests/check-qlist.o tests/check-qnull.o tests/check-qobject.o \ + tests/check-qjson.o tests/check-qlit.o \ + tests/check-block-qtest.o \ + tests/test-coroutine.o tests/test-string-output-visitor.o \ + tests/test-string-input-visitor.o tests/test-qobject-output-visitor.o \ + tests/test-clone-visitor.o \ + tests/test-qobject-input-visitor.o \ + tests/test-qmp-cmds.o tests/test-visitor-serialization.o \ + tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \ + tests/test-opts-visitor.o tests/test-qmp-event.o \ + tests/rcutorture.o tests/test-rcu-list.o \ + tests/test-rcu-simpleq.o \ + tests/test-rcu-tailq.o \ + tests/test-qdist.o tests/test-shift128.o \ + tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \ + tests/atomic_add-bench.o tests/atomic64-bench.o + +$(test-obj-y): QEMU_INCLUDES += -Itests +QEMU_CFLAGS += -I$(SRC_PATH)/tests + + +# Deps that are common to various different sets of tests below +test-util-obj-y = libqemuutil.a +test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y) +test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \ + tests/test-qapi-events.o tests/test-qapi-introspect.o \ + $(test-qom-obj-y) +benchmark-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-io-obj-y = $(io-obj-y) $(test-crypto-obj-y) +test-block-obj-y = $(block-obj-y) $(test-io-obj-y) tests/iothread.o + +tests/check-qnum$(EXESUF): tests/check-qnum.o $(test-util-obj-y) +tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y) +tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y) +tests/check-block-qdict$(EXESUF): tests/check-block-qdict.o $(test-util-obj-y) +tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y) +tests/check-qnull$(EXESUF): tests/check-qnull.o $(test-util-obj-y) +tests/check-qobject$(EXESUF): tests/check-qobject.o $(test-util-obj-y) +tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y) +tests/check-qlit$(EXESUF): tests/check-qlit.o $(test-util-obj-y) +tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y) +tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y) + +tests/test-char$(EXESUF): tests/test-char.o $(test-util-obj-y) $(qtest-obj-y) $(test-io-obj-y) $(chardev-obj-y) +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y) +tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y) +tests/test-aio-multithread$(EXESUF): tests/test-aio-multithread.o $(test-block-obj-y) +tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y) +tests/test-bdrv-drain$(EXESUF): tests/test-bdrv-drain.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-blockjob$(EXESUF): tests/test-blockjob.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-blockjob-txn$(EXESUF): tests/test-blockjob-txn.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-block-backend$(EXESUF): tests/test-block-backend.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-image-locking$(EXESUF): tests/test-image-locking.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y) +tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y) +tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) $(test-crypto-obj-y) +tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o +tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o migration/page_cache.o $(test-util-obj-y) +tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o $(test-util-obj-y) +tests/test-int128$(EXESUF): tests/test-int128.o +tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y) +tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y) +tests/test-rcu-simpleq$(EXESUF): tests/test-rcu-simpleq.o $(test-util-obj-y) +tests/test-rcu-tailq$(EXESUF): tests/test-rcu-tailq.o $(test-util-obj-y) +tests/test-qdist$(EXESUF): tests/test-qdist.o $(test-util-obj-y) +tests/test-qht$(EXESUF): tests/test-qht.o $(test-util-obj-y) +tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(test-util-obj-y) +tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y) +tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) +tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) +tests/atomic64-bench$(EXESUF): tests/atomic64-bench.o $(test-util-obj-y) + +tests/fp/%: + $(MAKE) -C $(dir $@) $(notdir $@) + +tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ + hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ + hw/core/bus.o \ + hw/core/irq.o \ + hw/core/fw-path-provider.o \ + hw/core/reset.o \ + $(test-qapi-obj-y) +tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ + migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ + migration/qemu-file-channel.o migration/qjson.o \ + $(test-io-obj-y) +tests/test-timed-average$(EXESUF): tests/test-timed-average.o $(test-util-obj-y) +tests/test-base64$(EXESUF): tests/test-base64.o $(test-util-obj-y) +tests/ptimer-test$(EXESUF): tests/ptimer-test.o tests/ptimer-test-stubs.o hw/core/ptimer.o + +tests/test-logging$(EXESUF): tests/test-logging.o $(test-util-obj-y) + +tests/test-replication$(EXESUF): tests/test-replication.o $(test-util-obj-y) \ + $(test-block-obj-y) + +tests/test-qapi-types.c tests/test-qapi-types.h \ +tests/test-qapi-visit.c tests/test-qapi-visit.h \ +tests/test-qapi-commands.h tests/test-qapi-commands.c \ +tests/test-qapi-events.c tests/test-qapi-events.h \ +tests/test-qapi-introspect.c tests/test-qapi-introspect.h: \ +tests/test-qapi-gen-timestamp ; +tests/test-qapi-gen-timestamp: $(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ + -o tests -p "test-" $<, \ + "GEN","$(@:%-timestamp=%)") + @>$@ + +tests/qapi-schema/doc-good.test.texi: $(SRC_PATH)/tests/qapi-schema/doc-good.json $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ + -o tests/qapi-schema -p "doc-good-" $<, \ + "GEN","$@") + @mv tests/qapi-schema/doc-good-qapi-doc.texi $@ + @rm -f tests/qapi-schema/doc-good-qapi-*.[ch] tests/qapi-schema/doc-good-qmp-*.[ch] + +tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) +tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y) +tests/test-qobject-output-visitor$(EXESUF): tests/test-qobject-output-visitor.o $(test-qapi-obj-y) +tests/test-clone-visitor$(EXESUF): tests/test-clone-visitor.o $(test-qapi-obj-y) +tests/test-qobject-input-visitor$(EXESUF): tests/test-qobject-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-cmds$(EXESUF): tests/test-qmp-cmds.o tests/test-qapi-commands.o $(test-qapi-obj-y) +tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y) +tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y) + +tests/test-shift128$(EXESUF): tests/test-shift128.o $(test-util-obj-y) +tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y) +tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y) +tests/test-bitcnt$(EXESUF): tests/test-bitcnt.o $(test-util-obj-y) +tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y) +tests/benchmark-crypto-hash$(EXESUF): tests/benchmark-crypto-hash.o $(test-crypto-obj-y) +tests/test-crypto-hmac$(EXESUF): tests/test-crypto-hmac.o $(test-crypto-obj-y) +tests/benchmark-crypto-hmac$(EXESUF): tests/benchmark-crypto-hmac.o $(test-crypto-obj-y) +tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y) +tests/benchmark-crypto-cipher$(EXESUF): tests/benchmark-crypto-cipher.o $(test-crypto-obj-y) +tests/test-crypto-secret$(EXESUF): tests/test-crypto-secret.o $(test-crypto-obj-y) +tests/test-crypto-xts$(EXESUF): tests/test-crypto-xts.o $(test-crypto-obj-y) + +tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS) +tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS) +tests/pkix_asn1_tab.o-cflags := $(TASN1_CFLAGS) + +tests/test-crypto-tlscredsx509.o-cflags := $(TASN1_CFLAGS) +tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) + +tests/test-crypto-tlssession.o-cflags := $(TASN1_CFLAGS) +tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \ + tests/crypto-tls-psk-helpers.o \ + $(test-crypto-obj-y) +tests/test-util-sockets$(EXESUF): tests/test-util-sockets.o \ + tests/socket-helpers.o $(test-util-obj-y) +tests/test-io-task$(EXESUF): tests/test-io-task.o $(test-io-obj-y) +tests/test-io-channel-socket$(EXESUF): tests/test-io-channel-socket.o \ + tests/io-channel-helpers.o tests/socket-helpers.o $(test-io-obj-y) +tests/tpm-crb-swtpm-test$(EXESUF): tests/tpm-crb-swtpm-test.o tests/tpm-emu.o \ + tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y) +tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o tests/tpm-emu.o $(test-io-obj-y) +tests/tpm-tis-swtpm-test$(EXESUF): tests/tpm-tis-swtpm-test.o tests/tpm-emu.o \ + tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y) +tests/tpm-tis-test$(EXESUF): tests/tpm-tis-test.o tests/tpm-emu.o $(test-io-obj-y) +tests/test-io-channel-file$(EXESUF): tests/test-io-channel-file.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-tls$(EXESUF): tests/test-io-channel-tls.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-command$(EXESUF): tests/test-io-channel-command.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-buffer$(EXESUF): tests/test-io-channel-buffer.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-crypto-pbkdf$(EXESUF): tests/test-crypto-pbkdf.o $(test-crypto-obj-y) +tests/test-crypto-ivgen$(EXESUF): tests/test-crypto-ivgen.o $(test-crypto-obj-y) +tests/test-crypto-afsplit$(EXESUF): tests/test-crypto-afsplit.o $(test-crypto-obj-y) +tests/test-crypto-block$(EXESUF): tests/test-crypto-block.o $(test-crypto-obj-y) + +libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o +libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o +libqos-spapr-obj-y = $(libqos-obj-y) tests/libqos/malloc-spapr.o +libqos-spapr-obj-y += tests/libqos/libqos-spapr.o +libqos-spapr-obj-y += tests/libqos/rtas.o +libqos-spapr-obj-y += tests/libqos/pci-spapr.o +libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o +libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o +libqos-pc-obj-y += tests/libqos/ahci.o +libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o +libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-usb-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/usb.o +libqos-virtio-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o + +tests/qmp-test$(EXESUF): tests/qmp-test.o +tests/qmp-cmd-test$(EXESUF): tests/qmp-cmd-test.o +tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o +tests/rtc-test$(EXESUF): tests/rtc-test.o +tests/m48t59-test$(EXESUF): tests/m48t59-test.o +tests/hexloader-test$(EXESUF): tests/hexloader-test.o +tests/endianness-test$(EXESUF): tests/endianness-test.o +tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) +tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) +tests/rtas-test$(EXESUF): tests/rtas-test.o $(libqos-spapr-obj-y) +tests/fdc-test$(EXESUF): tests/fdc-test.o +tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y) +tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) +tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o +tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o +tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o +tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y) +tests/boot-serial-test$(EXESUF): tests/boot-serial-test.o $(libqos-obj-y) +tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ + tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y) +tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) +tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) +tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) +tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o +tests/m25p80-test$(EXESUF): tests/m25p80-test.o +tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) +tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) +tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) +tests/e1000-test$(EXESUF): tests/e1000-test.o +tests/e1000e-test$(EXESUF): tests/e1000e-test.o $(libqos-pc-obj-y) +tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y) +tests/pcnet-test$(EXESUF): tests/pcnet-test.o +tests/pnv-xscom-test$(EXESUF): tests/pnv-xscom-test.o +tests/eepro100-test$(EXESUF): tests/eepro100-test.o +tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o +tests/ne2000-test$(EXESUF): tests/ne2000-test.o +tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o +tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y) +tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o $(libqos-virtio-obj-y) +tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y) +tests/virtio-ccw-test$(EXESUF): tests/virtio-ccw-test.o +tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y) +tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y) +tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y) +tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o $(libqos-virtio-obj-y) +tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o $(libqos-virtio-obj-y) +tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o $(libqos-virtio-obj-y) +tests/tpci200-test$(EXESUF): tests/tpci200-test.o +tests/display-vga-test$(EXESUF): tests/display-vga-test.o +tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o +tests/qom-test$(EXESUF): tests/qom-test.o +tests/test-hmp$(EXESUF): tests/test-hmp.o +tests/machine-none-test$(EXESUF): tests/machine-none-test.o +tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-virtio-obj-y) +tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y) +tests/nvme-test$(EXESUF): tests/nvme-test.o $(libqos-pc-obj-y) +tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o +tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o +tests/ac97-test$(EXESUF): tests/ac97-test.o +tests/es1370-test$(EXESUF): tests/es1370-test.o +tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o +tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y) +tests/cpu-plug-test$(EXESUF): tests/cpu-plug-test.o +tests/migration-test$(EXESUF): tests/migration-test.o +tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o $(test-util-obj-y) \ + $(qtest-obj-y) $(test-io-obj-y) $(libqos-virtio-obj-y) $(libqos-pc-obj-y) \ + $(chardev-obj-y) +tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o +tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y) +tests/test-keyval$(EXESUF): tests/test-keyval.o $(test-util-obj-y) $(test-qapi-obj-y) +tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y) +tests/test-netfilter$(EXESUF): tests/test-netfilter.o $(qtest-obj-y) +tests/test-filter-mirror$(EXESUF): tests/test-filter-mirror.o $(qtest-obj-y) +tests/test-filter-redirector$(EXESUF): tests/test-filter-redirector.o $(qtest-obj-y) +tests/test-x86-cpuid-compat$(EXESUF): tests/test-x86-cpuid-compat.o $(qtest-obj-y) +tests/ivshmem-test$(EXESUF): tests/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y) +tests/megasas-test$(EXESUF): tests/megasas-test.o $(libqos-spapr-obj-y) $(libqos-pc-obj-y) +tests/vhost-user-bridge$(EXESUF): tests/vhost-user-bridge.o $(test-util-obj-y) libvhost-user.a +tests/test-uuid$(EXESUF): tests/test-uuid.o $(test-util-obj-y) +tests/test-arm-mptimer$(EXESUF): tests/test-arm-mptimer.o +tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y) +tests/numa-test$(EXESUF): tests/numa-test.o +tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o +tests/sdhci-test$(EXESUF): tests/sdhci-test.o $(libqos-pc-obj-y) +tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y) + +tests/migration/stress$(EXESUF): tests/migration/stress.o + $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@") + +INITRD_WORK_DIR=tests/migration/initrd + +tests/migration/initrd-stress.img: tests/migration/stress$(EXESUF) + mkdir -p $(INITRD_WORK_DIR) + cp $< $(INITRD_WORK_DIR)/init + (cd $(INITRD_WORK_DIR) && (find | cpio --quiet -o -H newc | gzip -9)) > $@ + rm $(INITRD_WORK_DIR)/init + rmdir $(INITRD_WORK_DIR) + +ifeq ($(CONFIG_POSIX),y) +LIBS += -lutil +endif + +# QTest rules + +TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) +ifeq ($(CONFIG_POSIX),y) +QTEST_TARGETS = $(TARGETS) +check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y)) +check-qtest-y += $(check-qtest-generic-y) +else +QTEST_TARGETS = +endif + +qtest-obj-y = tests/libqtest.o $(test-util-obj-y) +$(check-qtest-y): $(qtest-obj-y) + +tests/test-qga$(EXESUF): qemu-ga$(EXESUF) +tests/test-qga$(EXESUF): tests/test-qga.o $(qtest-obj-y) + +SPEED = quick + +# gtester tests, possibly with verbose output +# do_test_tap runs all tests, even if some of them fail, while do_test_human +# stops at the first failure unless -k is given on the command line + +define do_test_human_k + $(quiet-@)rc=0; $(foreach COMMAND, $1, \ + $(call quiet-command-run, \ + export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only) \ + || rc=$$?;, "TEST", "$@: $(COMMAND)")) exit $$rc +endef +define do_test_human_no_k + $(foreach COMMAND, $1, \ + $(call quiet-command, \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2 \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only), \ + "TEST", "$@: $(COMMAND)") +) +endef +do_test_human = \ + $(if $(findstring k, $(MAKEFLAGS)), $(do_test_human_k), $(do_test_human_no_k)) + +define do_test_tap + $(call quiet-command, \ + { export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \ + $(foreach COMMAND, $1, \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | sed "s/^[a-z][a-z]* [0-9]* /&$(notdir $(COMMAND)) /" || true; ) } \ + | ./scripts/tap-merge.pl | tee "$@" \ + | ./scripts/tap-driver.pl $(if $(V),, --show-failures-only), \ + "TAP","$@") +endef + +.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS)) +$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: subdir-%-softmmu $(check-qtest-y) + $(call do_test_human,$(check-qtest-$*-y) $(check-qtest-generic-y), \ + QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF)) + +check-unit: $(check-unit-y) + $(call do_test_human, $^) + +check-speed: $(check-speed-y) + $(call do_test_human, $^) + +# gtester tests with TAP output + +$(patsubst %, check-report-qtest-%.tap, $(QTEST_TARGETS)): check-report-qtest-%.tap: $(check-qtest-y) + $(call do_test_tap, $(check-qtest-$*-y) $(check-qtest-generic-y), \ + QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF)) + +check-report-unit.tap: $(check-unit-y) + $(call do_test_tap,$^) + +# Reports and overall runs + +check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap + $(call quiet-command,./scripts/tap-merge.py $^ > $@,"GEN","$@") + +# Per guest TCG tests + +LINUX_USER_TARGETS=$(filter %-linux-user,$(TARGET_DIRS)) +BUILD_TCG_TARGET_RULES=$(patsubst %,build-tcg-tests-%, $(LINUX_USER_TARGETS)) +CLEAN_TCG_TARGET_RULES=$(patsubst %,clean-tcg-tests-%, $(LINUX_USER_TARGETS)) +RUN_TCG_TARGET_RULES=$(patsubst %,run-tcg-tests-%, $(LINUX_USER_TARGETS)) + +ifeq ($(HAVE_USER_DOCKER),y) +# Probe for the Docker Builds needed for each build +$(foreach PROBE_TARGET,$(TARGET_DIRS), \ + $(eval -include $(SRC_PATH)/tests/tcg/Makefile.probe) \ + $(if $(DOCKER_PREREQ), \ + $(eval build-tcg-tests-$(PROBE_TARGET): $(DOCKER_PREREQ)))) +endif + +build-tcg-tests-%: + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ + SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" guest-tests, \ + "BUILD", "TCG tests for $*") + +run-tcg-tests-%: % build-tcg-tests-% + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ + SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" run-guest-tests, \ + "RUN", "TCG tests for $*") + +clean-tcg-tests-%: + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" TARGET_DIR="$*/" clean-guest-tests,) + +.PHONY: build-tcg +build-tcg: $(BUILD_TCG_TARGET_RULES) + +.PHONY: check-tcg +check-tcg: $(RUN_TCG_TARGET_RULES) + +.PHONY: clean-tcg +clean-tcg: $(CLEAN_TCG_TARGET_RULES) + +# Other tests + +QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu-iotests/socket_scm_helper$(EXESUF) + +.PHONY: check-tests/qemu-iotests-quick.sh +check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) + $< + +.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) +$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json + $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \ + $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \ + $^ >$*.test.out 2>$*.test.err; \ + echo $$? >$*.test.exit, \ + "TEST","$*.out") + @# Sanitize error messages (make them independent of build directory) + @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -u $(SRC_PATH)/$*.err - + @diff -u $(SRC_PATH)/$*.out $*.test.out + @diff -u $(SRC_PATH)/$*.exit $*.test.exit + +.PHONY: check-tests/qapi-schema/doc-good.texi +check-tests/qapi-schema/doc-good.texi: tests/qapi-schema/doc-good.test.texi + @diff -u $(SRC_PATH)/tests/qapi-schema/doc-good.texi $< + +.PHONY: check-decodetree +check-decodetree: + $(call quiet-command, \ + cd $(SRC_PATH)/tests/decode && \ + ./check.sh "$(PYTHON)" "$(SRC_PATH)/scripts/decodetree.py", \ + TEST, decodetree.py) + +# Python venv for running tests + +.PHONY: check-venv check-acceptance + +TESTS_VENV_DIR=$(BUILD_DIR)/tests/venv +TESTS_VENV_REQ=$(SRC_PATH)/tests/requirements.txt +TESTS_RESULTS_DIR=$(BUILD_DIR)/tests/results +# Controls the output generated by Avocado when running tests. +# Any number of command separated loggers are accepted. For more +# information please refer to "avocado --help". +AVOCADO_SHOW=none + +PYTHON3 = $(shell $(PYTHON) -c 'import sys; print(1 if sys.version_info >= (3, 0) else 0)') +ifeq ($(PYTHON3), 1) +$(TESTS_VENV_DIR): $(TESTS_VENV_REQ) + $(call quiet-command, \ + $(PYTHON) -m venv --system-site-packages $@, \ + VENV, $@) + $(call quiet-command, \ + $(TESTS_VENV_DIR)/bin/python -m pip -q install -r $(TESTS_VENV_REQ), \ + PIP, $(TESTS_VENV_REQ)) + $(call quiet-command, touch $@) +else +$(TESTS_VENV_DIR): + $(error "venv directory for tests requires Python 3") +endif + +$(TESTS_RESULTS_DIR): + $(call quiet-command, mkdir -p $@, \ + MKDIR, $@) + +check-venv: $(TESTS_VENV_DIR) + +check-acceptance: check-venv $(TESTS_RESULTS_DIR) + $(call quiet-command, \ + $(TESTS_VENV_DIR)/bin/python -m avocado \ + --show=$(AVOCADO_SHOW) run --job-results-dir=$(TESTS_RESULTS_DIR) \ + --failfast=on $(SRC_PATH)/tests/acceptance, \ + "AVOCADO", "tests/acceptance") + +# Consolidated targets + +.PHONY: check-qapi-schema check-qtest check-unit check check-clean +check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) check-tests/qapi-schema/doc-good.texi +check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) +check-block: $(patsubst %,check-%, $(check-block-y)) +check: check-qapi-schema check-unit check-qtest check-decodetree +check-clean: + rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y) + rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y)) $(check-qtest-generic-y)) + rm -f tests/test-qapi-gen-timestamp + rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) + +clean: check-clean + +# Build the help program automatically + +all: $(QEMU_IOTESTS_HELPERS-y) + +-include $(wildcard tests/*.d) +-include $(wildcard tests/libqos/*.d) + +endif diff --git a/tests/Makefile.orig b/tests/Makefile.orig new file mode 100644 index 0000000000..e6474ba31b --- /dev/null +++ b/tests/Makefile.orig @@ -0,0 +1,569 @@ +export SRC_PATH + +qapi-py = $(SRC_PATH)/scripts/qapi.py $(SRC_PATH)/scripts/ordereddict.py + +# Get the list of all supported sysemu targets +SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \ + $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak))) + +check-unit-y = tests/check-qdict$(EXESUF) +gcov-files-check-qdict-y = qobject/qdict.c +check-unit-y += tests/check-qfloat$(EXESUF) +gcov-files-check-qfloat-y = qobject/qfloat.c +check-unit-y += tests/check-qint$(EXESUF) +gcov-files-check-qint-y = qobject/qint.c +check-unit-y += tests/check-qstring$(EXESUF) +gcov-files-check-qstring-y = qobject/qstring.c +check-unit-y += tests/check-qlist$(EXESUF) +gcov-files-check-qlist-y = qobject/qlist.c +check-unit-y += tests/check-qjson$(EXESUF) +gcov-files-check-qjson-y = qobject/qjson.c +check-unit-y += tests/test-qmp-output-visitor$(EXESUF) +gcov-files-test-qmp-output-visitor-y = qapi/qmp-output-visitor.c +check-unit-y += tests/test-qmp-input-visitor$(EXESUF) +gcov-files-test-qmp-input-visitor-y = qapi/qmp-input-visitor.c +check-unit-y += tests/test-qmp-input-strict$(EXESUF) +check-unit-y += tests/test-qmp-commands$(EXESUF) +gcov-files-test-qmp-commands-y = qapi/qmp-dispatch.c +check-unit-y += tests/test-string-input-visitor$(EXESUF) +gcov-files-test-string-input-visitor-y = qapi/string-input-visitor.c +check-unit-y += tests/test-string-output-visitor$(EXESUF) +gcov-files-test-string-output-visitor-y = qapi/string-output-visitor.c +check-unit-y += tests/test-qmp-event$(EXESUF) +gcov-files-test-qmp-event-y += qapi/qmp-event.c +check-unit-y += tests/test-opts-visitor$(EXESUF) +gcov-files-test-opts-visitor-y = qapi/opts-visitor.c +check-unit-y += tests/test-coroutine$(EXESUF) +gcov-files-test-coroutine-y = coroutine-$(CONFIG_COROUTINE_BACKEND).c +check-unit-y += tests/test-visitor-serialization$(EXESUF) +check-unit-y += tests/test-iov$(EXESUF) +gcov-files-test-iov-y = util/iov.c +check-unit-y += tests/test-aio$(EXESUF) +check-unit-$(CONFIG_POSIX) += tests/test-rfifolock$(EXESUF) +check-unit-y += tests/test-throttle$(EXESUF) +gcov-files-test-aio-$(CONFIG_WIN32) = aio-win32.c +gcov-files-test-aio-$(CONFIG_POSIX) = aio-posix.c +check-unit-y += tests/test-thread-pool$(EXESUF) +gcov-files-test-thread-pool-y = thread-pool.c +gcov-files-test-hbitmap-y = util/hbitmap.c +check-unit-y += tests/test-hbitmap$(EXESUF) +check-unit-y += tests/test-x86-cpuid$(EXESUF) +# all code tested by test-x86-cpuid is inside topology.h +gcov-files-test-x86-cpuid-y = +ifeq ($(CONFIG_SOFTMMU),y) +check-unit-y += tests/test-xbzrle$(EXESUF) +gcov-files-test-xbzrle-y = migration/xbzrle.c +check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) +endif +check-unit-y += tests/test-cutils$(EXESUF) +gcov-files-test-cutils-y += util/cutils.c +check-unit-y += tests/test-mul64$(EXESUF) +gcov-files-test-mul64-y = util/host-utils.c +check-unit-y += tests/test-int128$(EXESUF) +# all code tested by test-int128 is inside int128.h +gcov-files-test-int128-y = +check-unit-y += tests/rcutorture$(EXESUF) +gcov-files-rcutorture-y = util/rcu.c +check-unit-y += tests/test-rcu-list$(EXESUF) +gcov-files-test-rcu-list-y = util/rcu.c +check-unit-y += tests/test-bitops$(EXESUF) +check-unit-$(CONFIG_HAS_GLIB_SUBPROCESS_TESTS) += tests/test-qdev-global-props$(EXESUF) +check-unit-y += tests/check-qom-interface$(EXESUF) +gcov-files-check-qom-interface-y = qom/object.c +check-unit-y += tests/check-qom-proplist$(EXESUF) +gcov-files-check-qom-proplist-y = qom/object.c +check-unit-y += tests/test-qemu-opts$(EXESUF) +gcov-files-test-qemu-opts-y = qom/test-qemu-opts.c +check-unit-y += tests/test-write-threshold$(EXESUF) +gcov-files-test-write-threshold-y = block/write-threshold.c +check-unit-$(CONFIG_GNUTLS_HASH) += tests/test-crypto-hash$(EXESUF) +check-unit-y += tests/test-crypto-cipher$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF) + +check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh + +# All QTests for now are POSIX-only, but the dependencies are +# really in libqtest, not in the testcases themselves. + +gcov-files-ipack-y += hw/ipack/ipack.c +check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF) +gcov-files-ipack-y += hw/char/ipoctal232.c + +check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF) +gcov-files-virtioserial-y += hw/char/virtio-console.c + +gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio.c +check-qtest-virtio-y += tests/virtio-net-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/net/virtio-net.c +check-qtest-virtio-y += tests/virtio-balloon-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio-balloon.c +check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/block/virtio-blk.c +check-qtest-virtio-y += tests/virtio-rng-test$(EXESUF) +gcov-files-virtio-y += hw/virtio/virtio-rng.c +check-qtest-virtio-y += tests/virtio-scsi-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/scsi/virtio-scsi.c +ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy) +check-qtest-virtio-y += tests/virtio-9p-test$(EXESUF) +gcov-files-virtio-y += hw/9pfs/virtio-9p.c +gcov-files-virtio-y += i386-softmmu/hw/9pfs/virtio-9p-device.c +endif +check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/char/virtio-serial-bus.c +check-qtest-virtio-y += $(check-qtest-virtioserial-y) +gcov-files-virtio-y += $(gcov-files-virtioserial-y) + +check-qtest-pci-y += tests/e1000-test$(EXESUF) +gcov-files-pci-y += hw/net/e1000.c +check-qtest-pci-y += tests/rtl8139-test$(EXESUF) +gcov-files-pci-y += hw/net/rtl8139.c +check-qtest-pci-y += tests/pcnet-test$(EXESUF) +gcov-files-pci-y += hw/net/pcnet.c +gcov-files-pci-y += hw/net/pcnet-pci.c +check-qtest-pci-y += tests/eepro100-test$(EXESUF) +gcov-files-pci-y += hw/net/eepro100.c +check-qtest-pci-y += tests/ne2000-test$(EXESUF) +gcov-files-pci-y += hw/net/ne2000.c +check-qtest-pci-y += tests/nvme-test$(EXESUF) +gcov-files-pci-y += hw/block/nvme.c +check-qtest-pci-y += tests/ac97-test$(EXESUF) +gcov-files-pci-y += hw/audio/ac97.c +check-qtest-pci-y += tests/es1370-test$(EXESUF) +gcov-files-pci-y += hw/audio/es1370.c +check-qtest-pci-y += $(check-qtest-virtio-y) +gcov-files-pci-y += $(gcov-files-virtio-y) hw/virtio/virtio-pci.c +check-qtest-pci-y += tests/tpci200-test$(EXESUF) +gcov-files-pci-y += hw/ipack/tpci200.c +check-qtest-pci-y += $(check-qtest-ipack-y) +gcov-files-pci-y += $(gcov-files-ipack-y) +check-qtest-pci-y += tests/display-vga-test$(EXESUF) +gcov-files-pci-y += hw/display/vga.c +gcov-files-pci-y += hw/display/cirrus_vga.c +gcov-files-pci-y += hw/display/vga-pci.c +gcov-files-pci-y += hw/display/virtio-gpu.c +gcov-files-pci-y += hw/display/virtio-gpu-pci.c +gcov-files-pci-$(CONFIG_VIRTIO_VGA) += hw/display/virtio-vga.c +check-qtest-pci-y += tests/intel-hda-test$(EXESUF) +gcov-files-pci-y += hw/audio/intel-hda.c hw/audio/hda-codec.c + +check-qtest-i386-y = tests/endianness-test$(EXESUF) +check-qtest-i386-y += tests/fdc-test$(EXESUF) +gcov-files-i386-y = hw/block/fdc.c +check-qtest-i386-y += tests/ide-test$(EXESUF) +check-qtest-i386-y += tests/ahci-test$(EXESUF) +check-qtest-i386-y += tests/hd-geo-test$(EXESUF) +gcov-files-i386-y += hw/block/hd-geometry.c +check-qtest-i386-y += tests/boot-order-test$(EXESUF) +check-qtest-i386-y += tests/bios-tables-test$(EXESUF) +check-qtest-i386-y += tests/rtc-test$(EXESUF) +check-qtest-i386-y += tests/i440fx-test$(EXESUF) +check-qtest-i386-y += tests/fw_cfg-test$(EXESUF) +check-qtest-i386-y += tests/drive_del-test$(EXESUF) +check-qtest-i386-y += tests/wdt_ib700-test$(EXESUF) +check-qtest-i386-y += tests/tco-test$(EXESUF) +gcov-files-i386-y += hw/watchdog/watchdog.c hw/watchdog/wdt_ib700.c +check-qtest-i386-y += $(check-qtest-pci-y) +gcov-files-i386-y += $(gcov-files-pci-y) +check-qtest-i386-y += tests/vmxnet3-test$(EXESUF) +gcov-files-i386-y += hw/net/vmxnet3.c +gcov-files-i386-y += hw/net/vmxnet_rx_pkt.c +gcov-files-i386-y += hw/net/vmxnet_tx_pkt.c +check-qtest-i386-y += tests/pvpanic-test$(EXESUF) +gcov-files-i386-y += i386-softmmu/hw/misc/pvpanic.c +check-qtest-i386-y += tests/i82801b11-test$(EXESUF) +gcov-files-i386-y += hw/pci-bridge/i82801b11.c +check-qtest-i386-y += tests/ioh3420-test$(EXESUF) +gcov-files-i386-y += hw/pci-bridge/ioh3420.c +check-qtest-i386-y += tests/usb-hcd-ohci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-ohci.c +check-qtest-i386-y += tests/usb-hcd-uhci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-uhci.c +check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-ehci.c +gcov-files-i386-y += hw/usb/dev-hid.c +gcov-files-i386-y += hw/usb/dev-storage.c +check-qtest-i386-y += tests/usb-hcd-xhci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-xhci.c +check-qtest-i386-y += tests/pc-cpu-test$(EXESUF) +check-qtest-i386-y += tests/q35-test$(EXESUF) +gcov-files-i386-y += hw/pci-host/q35.c +ifeq ($(CONFIG_VHOST_NET),y) +check-qtest-i386-$(CONFIG_LINUX) += tests/vhost-user-test$(EXESUF) +endif +check-qtest-x86_64-y = $(check-qtest-i386-y) +gcov-files-i386-y += i386-softmmu/hw/timer/mc146818rtc.c +gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y)) +check-qtest-mips-y = tests/endianness-test$(EXESUF) +check-qtest-mips64-y = tests/endianness-test$(EXESUF) +check-qtest-mips64el-y = tests/endianness-test$(EXESUF) +check-qtest-ppc-y = tests/endianness-test$(EXESUF) +check-qtest-ppc64-y = tests/endianness-test$(EXESUF) +check-qtest-sh4-y = tests/endianness-test$(EXESUF) +check-qtest-sh4eb-y = tests/endianness-test$(EXESUF) +check-qtest-sparc64-y = tests/endianness-test$(EXESUF) +#check-qtest-sparc-y = tests/m48t59-test$(EXESUF) +#check-qtest-sparc64-y += tests/m48t59-test$(EXESUF) +gcov-files-sparc-y += hw/timer/m48t59.c +gcov-files-sparc64-y += hw/timer/m48t59.c +check-qtest-arm-y = tests/tmp105-test$(EXESUF) +check-qtest-arm-y = tests/ds1338-test$(EXESUF) +gcov-files-arm-y += hw/misc/tmp105.c +check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) +gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c +check-qtest-ppc-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc64-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF) +gcov-files-ppc64-y += ppc64-softmmu/hw/ppc/spapr_pci.c +check-qtest-microblazeel-y = $(check-qtest-microblaze-y) +check-qtest-xtensaeb-y = $(check-qtest-xtensa-y) + +# qom-test works for all sysemu architectures: +$(foreach target,$(SYSEMU_TARGET_LIST), \ + $(if $(findstring tests/qom-test$(EXESUF), $(check-qtest-$(target)-y)),, \ + $(eval check-qtest-$(target)-y += tests/qom-test$(EXESUF)))) + +check-qapi-schema-y := $(addprefix tests/qapi-schema/, \ + comments.json empty.json enum-empty.json enum-missing-data.json \ + enum-wrong-data.json enum-int-member.json enum-dict-member.json \ + enum-clash-member.json enum-max-member.json enum-union-clash.json \ + enum-bad-name.json enum-bad-prefix.json \ + funny-char.json indented-expr.json \ + missing-type.json bad-ident.json ident-with-escape.json \ + escape-outside-string.json unknown-escape.json \ + escape-too-short.json escape-too-big.json unicode-str.json \ + double-type.json bad-base.json bad-type-bool.json bad-type-int.json \ + bad-type-dict.json double-data.json unknown-expr-key.json \ + redefined-type.json redefined-command.json redefined-builtin.json \ + redefined-event.json command-int.json bad-data.json event-max.json \ + type-bypass-bad-gen.json \ + args-invalid.json \ + args-array-empty.json args-array-unknown.json args-int.json \ + args-unknown.json args-member-unknown.json args-member-array.json \ + args-member-array-bad.json args-alternate.json args-union.json \ + args-any.json \ + returns-array-bad.json returns-int.json returns-dict.json \ + returns-unknown.json returns-alternate.json returns-whitelist.json \ + missing-colon.json missing-comma-list.json missing-comma-object.json \ + struct-data-invalid.json struct-member-invalid.json \ + nested-struct-data.json non-objects.json \ + qapi-schema-test.json quoted-structural-chars.json \ + leading-comma-list.json leading-comma-object.json \ + trailing-comma-list.json trailing-comma-object.json \ + unclosed-list.json unclosed-object.json unclosed-string.json \ + duplicate-key.json union-invalid-base.json union-bad-branch.json \ + union-optional-branch.json union-unknown.json union-max.json \ + flat-union-optional-discriminator.json flat-union-no-base.json \ + flat-union-invalid-discriminator.json flat-union-inline.json \ + flat-union-invalid-branch-key.json flat-union-reverse-define.json \ + flat-union-string-discriminator.json union-base-no-discriminator.json \ + flat-union-bad-discriminator.json flat-union-bad-base.json \ + flat-union-base-any.json \ + flat-union-array-branch.json flat-union-int-branch.json \ + flat-union-base-union.json flat-union-branch-clash.json \ + alternate-nested.json alternate-unknown.json alternate-clash.json \ + alternate-good.json alternate-base.json alternate-array.json \ + alternate-conflict-string.json alternate-conflict-dict.json \ + include-simple.json include-relpath.json include-format-err.json \ + include-non-file.json include-no-file.json include-before-err.json \ + include-nested-err.json include-self-cycle.json include-cycle.json \ + include-repetition.json event-nest-struct.json event-case.json \ + struct-base-clash.json struct-base-clash-deep.json ) + +GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h \ + tests/test-qmp-commands.h tests/test-qapi-event.h \ + tests/test-qmp-introspect.h + +test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \ + tests/check-qlist.o tests/check-qfloat.o tests/check-qjson.o \ + tests/test-coroutine.o tests/test-string-output-visitor.o \ + tests/test-string-input-visitor.o tests/test-qmp-output-visitor.o \ + tests/test-qmp-input-visitor.o tests/test-qmp-input-strict.o \ + tests/test-qmp-commands.o tests/test-visitor-serialization.o \ + tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \ + tests/test-opts-visitor.o tests/test-qmp-event.o \ + tests/rcutorture.o tests/test-rcu-list.o + +$(test-obj-y): QEMU_INCLUDES += -Itests +QEMU_CFLAGS += -I$(SRC_PATH)/tests + + +# Deps that are common to various different sets of tests below +test-util-obj-y = libqemuutil.a libqemustub.a +test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y) +test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \ + tests/test-qapi-event.o tests/test-qmp-introspect.o \ + $(test-qom-obj-y) +test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-block-obj-y = $(block-obj-y) $(test-crypto-obj-y) + +tests/check-qint$(EXESUF): tests/check-qint.o $(test-util-obj-y) +tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y) +tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y) +tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y) +tests/check-qfloat$(EXESUF): tests/check-qfloat.o $(test-util-obj-y) +tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y) +tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y) +tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y) +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y) +tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y) +tests/test-rfifolock$(EXESUF): tests/test-rfifolock.o $(test-util-obj-y) +tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y) +tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y) +tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y) +tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) +tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o +tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o page_cache.o $(test-util-obj-y) +tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o +tests/test-int128$(EXESUF): tests/test-int128.o +tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y) +tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y) + +tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ + hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ + hw/core/irq.o \ + hw/core/fw-path-provider.o \ + $(test-qapi-obj-y) +tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ + migration/vmstate.o migration/qemu-file.o migration/qemu-file-buf.o \ + migration/qemu-file-unix.o qjson.o \ + $(test-qom-obj-y) + +tests/test-qapi-types.c tests/test-qapi-types.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-types.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-types.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qapi-visit.c tests/test-qapi-visit.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-visit.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-visit.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qmp-commands.h tests/test-qmp-marshal.c :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qapi-event.c tests/test-qapi-event.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-event.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-event.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qmp-introspect.c tests/test-qmp-introspect.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-introspect.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-introspect.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") + +tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) +tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y) +tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) +tests/test-qmp-input-visitor$(EXESUF): tests/test-qmp-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-input-strict$(EXESUF): tests/test-qmp-input-strict.o $(test-qapi-obj-y) +tests/test-qmp-commands$(EXESUF): tests/test-qmp-commands.o tests/test-qmp-marshal.o $(test-qapi-obj-y) +tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y) +tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y) + +tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y) +tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y) +tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y) +tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y) +tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) +tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) + +libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o +libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o +libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o +libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o +libqos-pc-obj-y += tests/libqos/ahci.o +libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o +libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-usb-obj-y = $(libqos-pc-obj-y) tests/libqos/usb.o +libqos-virtio-obj-y = $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o + +tests/rtc-test$(EXESUF): tests/rtc-test.o +tests/m48t59-test$(EXESUF): tests/m48t59-test.o +tests/endianness-test$(EXESUF): tests/endianness-test.o +tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) +tests/fdc-test$(EXESUF): tests/fdc-test.o +tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y) +tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) +tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o +tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y) +tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y) +tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) +tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) +tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) +tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) +tests/e1000-test$(EXESUF): tests/e1000-test.o +tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y) +tests/pcnet-test$(EXESUF): tests/pcnet-test.o +tests/eepro100-test$(EXESUF): tests/eepro100-test.o +tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o +tests/ne2000-test$(EXESUF): tests/ne2000-test.o +tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o +tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y) +tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o +tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y) +tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y) +tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y) +tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y) +tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o +tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o +tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o +tests/tpci200-test$(EXESUF): tests/tpci200-test.o +tests/display-vga-test$(EXESUF): tests/display-vga-test.o +tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o +tests/qom-test$(EXESUF): tests/qom-test.o +tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-pc-obj-y) +tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y) +tests/nvme-test$(EXESUF): tests/nvme-test.o +tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o +tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o +tests/ac97-test$(EXESUF): tests/ac97-test.o +tests/es1370-test$(EXESUF): tests/es1370-test.o +tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o +tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y) +tests/pc-cpu-test$(EXESUF): tests/pc-cpu-test.o +tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o qemu-char.o qemu-timer.o $(qtest-obj-y) +tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o +tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y) +tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y) + +ifeq ($(CONFIG_POSIX),y) +LIBS += -lutil +endif +LIBS += $(TEST_LIBS) +CFLAGS += $(TEST_CFLAGS) + +# QTest rules + +TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) +ifeq ($(CONFIG_POSIX),y) +QTEST_TARGETS=$(foreach TARGET,$(TARGETS), $(if $(check-qtest-$(TARGET)-y), $(TARGET),)) +check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y)) +endif + +qtest-obj-y = tests/libqtest.o $(test-util-obj-y) +$(check-qtest-y): $(qtest-obj-y) + +.PHONY: check-help +check-help: + @echo "Regression testing targets:" + @echo + @echo " make check Run all tests" + @echo " make check-qtest-TARGET Run qtest tests for given target" + @echo " make check-qtest Run qtest tests" + @echo " make check-unit Run qobject tests" + @echo " make check-qapi-schema Run QAPI schema tests" + @echo " make check-block Run block tests" + @echo " make check-report.html Generates an HTML test report" + @echo " make check-clean Clean the tests" + @echo + @echo "Please note that HTML reports do not regenerate if the unit tests" + @echo "has not changed." + @echo + @echo "The variable SPEED can be set to control the gtester speed setting." + @echo "Default options are -k and (for make V=1) --verbose; they can be" + @echo "changed with variable GTESTER_OPTIONS." + +SPEED = quick +GTESTER_OPTIONS = -k $(if $(V),--verbose,-q) +GCOV_OPTIONS = -n $(if $(V),-f,) + +# gtester tests, possibly with verbose output + +.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS)) +$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: $(check-qtest-y) + $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,) + $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF) \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \ + gtester $(GTESTER_OPTIONS) -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@") + $(if $(CONFIG_GCOV),@for f in $(gcov-files-$*-y); do \ + echo Gcov report for $$f:;\ + $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \ + done,) + +.PHONY: $(patsubst %, check-%, $(check-unit-y)) +$(patsubst %, check-%, $(check-unit-y)): check-%: % + $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,) + $(call quiet-command, \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \ + gtester $(GTESTER_OPTIONS) -m=$(SPEED) $*,"GTESTER $*") + $(if $(CONFIG_GCOV),@for f in $(gcov-files-$(subst tests/,,$*)-y); do \ + echo Gcov report for $$f:;\ + $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \ + done,) + +# gtester tests with XML output + +$(patsubst %, check-report-qtest-%.xml, $(QTEST_TARGETS)): check-report-qtest-%.xml: $(check-qtest-y) + $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF) \ + gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@") + +check-report-unit.xml: $(check-unit-y) + $(call quiet-command,gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $^, "GTESTER $@") + +# Reports and overall runs + +check-report.xml: $(patsubst %,check-report-qtest-%.xml, $(QTEST_TARGETS)) check-report-unit.xml + $(call quiet-command,$(SRC_PATH)/scripts/gtester-cat $^ > $@, " GEN $@") + +check-report.html: check-report.xml + $(call quiet-command,gtester-report $< > $@, " GEN $@") + + +# Other tests + +QEMU_IOTESTS_HELPERS-$(CONFIG_LINUX) = tests/qemu-iotests/socket_scm_helper$(EXESUF) + +.PHONY: check-tests/qemu-iotests-quick.sh +check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) + $< + +.PHONY: check-tests/test-qapi.py +check-tests/test-qapi.py: tests/test-qapi.py + +.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) +$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json + $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \ + $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \ + $^ >$*.test.out 2>$*.test.err; \ + echo $$? >$*.test.exit, \ + " TEST $*.out") + @diff -q $(SRC_PATH)/$*.out $*.test.out + @# Sanitize error messages (make them independent of build directory) + @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -q $(SRC_PATH)/$*.err - + @diff -q $(SRC_PATH)/$*.exit $*.test.exit + +# Consolidated targets + +.PHONY: check-qapi-schema check-qtest check-unit check check-clean +check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) +check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) +check-unit: $(patsubst %,check-%, $(check-unit-y)) +check-block: $(patsubst %,check-%, $(check-block-y)) +check: check-qapi-schema check-unit check-qtest +check-clean: + $(MAKE) -C tests/tcg clean + rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y) + rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y))) + +clean: check-clean + +# Build the help program automatically + +all: $(QEMU_IOTESTS_HELPERS-y) + +-include $(wildcard tests/*.d) +-include $(wildcard tests/libqos/*.d) diff --git a/tests/bios-tables-test.c.orig b/tests/bios-tables-test.c.orig new file mode 100644 index 0000000000..d455b2abfc --- /dev/null +++ b/tests/bios-tables-test.c.orig @@ -0,0 +1,925 @@ +/* + * Boot order test cases. + * + * Copyright (c) 2013 Red Hat Inc. + * + * Authors: + * Michael S. Tsirkin , + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include +#include "qemu-common.h" +#include "hw/firmware/smbios.h" +#include "qemu/bitmap.h" +#include "acpi-utils.h" +#include "boot-sector.h" + +#define MACHINE_PC "pc" +#define MACHINE_Q35 "q35" + +#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" + +typedef struct { + const char *machine; + const char *variant; + uint32_t rsdp_addr; + uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */]; + AcpiRsdtDescriptorRev1 rsdt_table; + uint32_t dsdt_addr; + uint32_t facs_addr; + AcpiFacsDescriptorRev1 facs_table; + uint32_t *rsdt_tables_addr; + int rsdt_tables_nr; + GArray *tables; + uint32_t smbios_ep_addr; + struct smbios_21_entry_point smbios_ep_table; + uint8_t *required_struct_types; + int required_struct_types_len; + QTestState *qts; +} test_data; + +static char disk[] = "tests/acpi-test-disk-XXXXXX"; +static const char *data_dir = "tests/data/acpi"; +#ifdef CONFIG_IASL +static const char *iasl = stringify(CONFIG_IASL); +#else +static const char *iasl; +#endif + +static void free_test_data(test_data *data) +{ + AcpiSdtTable *temp; + int i; + + g_free(data->rsdt_tables_addr); + + for (i = 0; i < data->tables->len; ++i) { + temp = &g_array_index(data->tables, AcpiSdtTable, i); + g_free(temp->aml); + if (temp->aml_file && + !temp->tmp_files_retain && + g_strstr_len(temp->aml_file, -1, "aml-")) { + unlink(temp->aml_file); + } + g_free(temp->aml_file); + g_free(temp->asl); + if (temp->asl_file && + !temp->tmp_files_retain) { + unlink(temp->asl_file); + } + g_free(temp->asl_file); + } + + g_array_free(data->tables, true); +} + +static void test_acpi_rsdp_address(test_data *data) +{ + uint32_t off = acpi_find_rsdp_address(data->qts); + g_assert_cmphex(off, <, 0x100000); + data->rsdp_addr = off; +} + +static void test_acpi_rsdp_table(test_data *data) +{ + uint8_t *rsdp_table = data->rsdp_table, revision; + uint32_t addr = data->rsdp_addr; + + acpi_parse_rsdp_table(data->qts, addr, rsdp_table); + revision = rsdp_table[15 /* Revision offset */]; + + switch (revision) { + case 0: /* ACPI 1.0 RSDP */ + /* With rev 1, checksum is only for the first 20 bytes */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + break; + case 2: /* ACPI 2.0+ RSDP */ + /* With revision 2, we have 2 checksums */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + g_assert(!acpi_calc_checksum(rsdp_table, 36)); + break; + default: + g_assert_not_reached(); + } +} + +static void test_acpi_rsdt_table(test_data *data) +{ + AcpiRsdtDescriptorRev1 *rsdt_table = &data->rsdt_table; + uint32_t addr = acpi_get_rsdt_address(data->rsdp_table); + uint32_t *tables; + int tables_nr; + uint8_t checksum; + uint32_t rsdt_table_length; + + /* read the header */ + ACPI_READ_TABLE_HEADER(data->qts, rsdt_table, addr); + ACPI_ASSERT_CMP(rsdt_table->signature, "RSDT"); + + rsdt_table_length = le32_to_cpu(rsdt_table->length); + + /* compute the table entries in rsdt */ + tables_nr = (rsdt_table_length - sizeof(AcpiRsdtDescriptorRev1)) / + sizeof(uint32_t); + g_assert(tables_nr > 0); + + /* get the addresses of the tables pointed by rsdt */ + tables = g_new0(uint32_t, tables_nr); + ACPI_READ_ARRAY_PTR(data->qts, tables, tables_nr, addr); + + checksum = acpi_calc_checksum((uint8_t *)rsdt_table, rsdt_table_length) + + acpi_calc_checksum((uint8_t *)tables, + tables_nr * sizeof(uint32_t)); + g_assert(!checksum); + + /* SSDT tables after FADT */ + data->rsdt_tables_addr = tables; + data->rsdt_tables_nr = tables_nr; +} + +static void fadt_fetch_facs_and_dsdt_ptrs(test_data *data) +{ + uint32_t addr; + AcpiTableHeader hdr; + + /* FADT table comes first */ + addr = le32_to_cpu(data->rsdt_tables_addr[0]); + ACPI_READ_TABLE_HEADER(data->qts, &hdr, addr); + ACPI_ASSERT_CMP(hdr.signature, "FACP"); + + ACPI_READ_FIELD(data->qts, data->facs_addr, addr); + ACPI_READ_FIELD(data->qts, data->dsdt_addr, addr); +} + +static void sanitize_fadt_ptrs(test_data *data) +{ + /* fixup pointers in FADT */ + int i; + + for (i = 0; i < data->tables->len; i++) { + AcpiSdtTable *sdt = &g_array_index(data->tables, AcpiSdtTable, i); + + if (memcmp(&sdt->header.signature, "FACP", 4)) { + continue; + } + + /* check original FADT checksum before sanitizing table */ + g_assert(!(uint8_t)( + acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len) + )); + + /* sdt->aml field offset := spec offset - header size */ + memset(sdt->aml + 0, 0, 4); /* sanitize FIRMWARE_CTRL(36) ptr */ + memset(sdt->aml + 4, 0, 4); /* sanitize DSDT(40) ptr */ + if (sdt->header.revision >= 3) { + memset(sdt->aml + 96, 0, 8); /* sanitize X_FIRMWARE_CTRL(132) ptr */ + memset(sdt->aml + 104, 0, 8); /* sanitize X_DSDT(140) ptr */ + } + + /* update checksum */ + sdt->header.checksum = 0; + sdt->header.checksum -= + acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len); + break; + } +} + +static void test_acpi_facs_table(test_data *data) +{ + AcpiFacsDescriptorRev1 *facs_table = &data->facs_table; + uint32_t addr = le32_to_cpu(data->facs_addr); + + ACPI_READ_FIELD(data->qts, facs_table->signature, addr); + ACPI_READ_FIELD(data->qts, facs_table->length, addr); + ACPI_READ_FIELD(data->qts, facs_table->hardware_signature, addr); + ACPI_READ_FIELD(data->qts, facs_table->firmware_waking_vector, addr); + ACPI_READ_FIELD(data->qts, facs_table->global_lock, addr); + ACPI_READ_FIELD(data->qts, facs_table->flags, addr); + ACPI_READ_ARRAY(data->qts, facs_table->resverved3, addr); + + ACPI_ASSERT_CMP(facs_table->signature, "FACS"); +} + +/** fetch_table + * load ACPI table at @addr into table descriptor @sdt_table + * and check that header checksum matches actual one. + */ +static void fetch_table(QTestState *qts, AcpiSdtTable *sdt_table, uint32_t addr) +{ + uint8_t checksum; + + memset(sdt_table, 0, sizeof(*sdt_table)); + ACPI_READ_TABLE_HEADER(qts, &sdt_table->header, addr); + + sdt_table->aml_len = le32_to_cpu(sdt_table->header.length) + - sizeof(AcpiTableHeader); + sdt_table->aml = g_malloc0(sdt_table->aml_len); + ACPI_READ_ARRAY_PTR(qts, sdt_table->aml, sdt_table->aml_len, addr); + + checksum = acpi_calc_checksum((uint8_t *)sdt_table, + sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt_table->aml, + sdt_table->aml_len); + g_assert(!checksum); +} + +static void test_acpi_dsdt_table(test_data *data) +{ + AcpiSdtTable dsdt_table; + uint32_t addr = le32_to_cpu(data->dsdt_addr); + + fetch_table(data->qts, &dsdt_table, addr); + ACPI_ASSERT_CMP(dsdt_table.header.signature, "DSDT"); + + /* Since DSDT isn't in RSDT, add DSDT to ASL test tables list manually */ + g_array_append_val(data->tables, dsdt_table); +} + +/* Load all tables and add to test list directly RSDT referenced tables */ +static void fetch_rsdt_referenced_tables(test_data *data) +{ + int tables_nr = data->rsdt_tables_nr; + int i; + + for (i = 0; i < tables_nr; i++) { + AcpiSdtTable ssdt_table; + uint32_t addr; + + addr = le32_to_cpu(data->rsdt_tables_addr[i]); + fetch_table(data->qts, &ssdt_table, addr); + + /* Add table to ASL test tables list */ + g_array_append_val(data->tables, ssdt_table); + } +} + +static void dump_aml_files(test_data *data, bool rebuild) +{ + AcpiSdtTable *sdt; + GError *error = NULL; + gchar *aml_file = NULL; + gint fd; + ssize_t ret; + int i; + + for (i = 0; i < data->tables->len; ++i) { + const char *ext = data->variant ? data->variant : ""; + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + g_assert(sdt->aml); + + if (rebuild) { + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + (gchar *)&sdt->header.signature, ext); + fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT, + S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); + } else { + fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error); + g_assert_no_error(error); + } + g_assert(fd >= 0); + + ret = qemu_write_full(fd, sdt, sizeof(AcpiTableHeader)); + g_assert(ret == sizeof(AcpiTableHeader)); + ret = qemu_write_full(fd, sdt->aml, sdt->aml_len); + g_assert(ret == sdt->aml_len); + + close(fd); + + g_free(aml_file); + } +} + +static bool compare_signature(AcpiSdtTable *sdt, const char *signature) +{ + return !memcmp(&sdt->header.signature, signature, 4); +} + +static bool load_asl(GArray *sdts, AcpiSdtTable *sdt) +{ + AcpiSdtTable *temp; + GError *error = NULL; + GString *command_line = g_string_new(iasl); + gint fd; + gchar *out, *out_err; + gboolean ret; + int i; + + fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error); + g_assert_no_error(error); + close(fd); + + /* build command line */ + g_string_append_printf(command_line, " -p %s ", sdt->asl_file); + if (compare_signature(sdt, "DSDT") || + compare_signature(sdt, "SSDT")) { + for (i = 0; i < sdts->len; ++i) { + temp = &g_array_index(sdts, AcpiSdtTable, i); + if (compare_signature(temp, "DSDT") || + compare_signature(temp, "SSDT")) { + g_string_append_printf(command_line, "-e %s ", temp->aml_file); + } + } + } + g_string_append_printf(command_line, "-d %s", sdt->aml_file); + + /* pass 'out' and 'out_err' in order to be redirected */ + ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error); + g_assert_no_error(error); + if (ret) { + ret = g_file_get_contents(sdt->asl_file, &sdt->asl, + &sdt->asl_len, &error); + g_assert(ret); + g_assert_no_error(error); + ret = (sdt->asl_len > 0); + } + + g_free(out); + g_free(out_err); + g_string_free(command_line, true); + + return !ret; +} + +#define COMMENT_END "*/" +#define DEF_BLOCK "DefinitionBlock (" +#define BLOCK_NAME_END "," + +static GString *normalize_asl(gchar *asl_code) +{ + GString *asl = g_string_new(asl_code); + gchar *comment, *block_name; + + /* strip comments (different generation days) */ + comment = g_strstr_len(asl->str, asl->len, COMMENT_END); + if (comment) { + comment += strlen(COMMENT_END); + while (*comment == '\n') { + comment++; + } + asl = g_string_erase(asl, 0, comment - asl->str); + } + + /* strip def block name (it has file path in it) */ + if (g_str_has_prefix(asl->str, DEF_BLOCK)) { + block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END); + g_assert(block_name); + asl = g_string_erase(asl, 0, + block_name + sizeof(BLOCK_NAME_END) - asl->str); + } + + return asl; +} + +static GArray *load_expected_aml(test_data *data) +{ + int i; + AcpiSdtTable *sdt; + GError *error = NULL; + gboolean ret; + + GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + if (getenv("V")) { + fputc('\n', stderr); + } + for (i = 0; i < data->tables->len; ++i) { + AcpiSdtTable exp_sdt; + gchar *aml_file = NULL; + const char *ext = data->variant ? data->variant : ""; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + + memset(&exp_sdt, 0, sizeof(exp_sdt)); + exp_sdt.header.signature = sdt->header.signature; + +try_again: + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + (gchar *)&sdt->header.signature, ext); + if (getenv("V")) { + fprintf(stderr, "Looking for expected file '%s'\n", aml_file); + } + if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) { + exp_sdt.aml_file = aml_file; + } else if (*ext != '\0') { + /* try fallback to generic (extension less) expected file */ + ext = ""; + g_free(aml_file); + goto try_again; + } + g_assert(exp_sdt.aml_file); + if (getenv("V")) { + fprintf(stderr, "Using expected file '%s'\n", aml_file); + } + ret = g_file_get_contents(aml_file, &exp_sdt.aml, + &exp_sdt.aml_len, &error); + g_assert(ret); + g_assert_no_error(error); + g_assert(exp_sdt.aml); + g_assert(exp_sdt.aml_len); + + g_array_append_val(exp_tables, exp_sdt); + } + + return exp_tables; +} + +/* test the list of tables in @data->tables against reference tables */ +static void test_acpi_asl(test_data *data) +{ + int i; + AcpiSdtTable *sdt, *exp_sdt; + test_data exp_data; + gboolean exp_err, err; + + memset(&exp_data, 0, sizeof(exp_data)); + exp_data.tables = load_expected_aml(data); + dump_aml_files(data, false); + for (i = 0; i < data->tables->len; ++i) { + GString *asl, *exp_asl; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i); + + err = load_asl(data->tables, sdt); + asl = normalize_asl(sdt->asl); + + exp_err = load_asl(exp_data.tables, exp_sdt); + exp_asl = normalize_asl(exp_sdt->asl); + + /* TODO: check for warnings */ + g_assert(!err || exp_err); + + if (g_strcmp0(asl->str, exp_asl->str)) { + if (exp_err) { + fprintf(stderr, + "Warning! iasl couldn't parse the expected aml\n"); + } else { + uint32_t signature = cpu_to_le32(exp_sdt->header.signature); + sdt->tmp_files_retain = true; + exp_sdt->tmp_files_retain = true; + fprintf(stderr, + "acpi-test: Warning! %.4s mismatch. " + "Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n", + (gchar *)&signature, + sdt->asl_file, sdt->aml_file, + exp_sdt->asl_file, exp_sdt->aml_file); + if (getenv("V")) { + const char *diff_cmd = getenv("DIFF"); + if (diff_cmd) { + int ret G_GNUC_UNUSED; + char *diff = g_strdup_printf("%s %s %s", diff_cmd, + exp_sdt->asl_file, sdt->asl_file); + ret = system(diff) ; + g_free(diff); + } else { + fprintf(stderr, "acpi-test: Warning. not showing " + "difference since no diff utility is specified. " + "Set 'DIFF' environment variable to a preferred " + "diff utility and run 'make V=1 check' again to " + "see ASL difference."); + } + } + } + } + g_string_free(asl, true); + g_string_free(exp_asl, true); + } + + free_test_data(&exp_data); +} + +static bool smbios_ep_table_ok(test_data *data) +{ + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = data->smbios_ep_addr; + + ACPI_READ_ARRAY(data->qts, ep_table->anchor_string, addr); + if (memcmp(ep_table->anchor_string, "_SM_", 4)) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->checksum, addr); + ACPI_READ_FIELD(data->qts, ep_table->length, addr); + ACPI_READ_FIELD(data->qts, ep_table->smbios_major_version, addr); + ACPI_READ_FIELD(data->qts, ep_table->smbios_minor_version, addr); + ACPI_READ_FIELD(data->qts, ep_table->max_structure_size, addr); + ACPI_READ_FIELD(data->qts, ep_table->entry_point_revision, addr); + ACPI_READ_ARRAY(data->qts, ep_table->formatted_area, addr); + ACPI_READ_ARRAY(data->qts, ep_table->intermediate_anchor_string, addr); + if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->intermediate_checksum, addr); + ACPI_READ_FIELD(data->qts, ep_table->structure_table_length, addr); + if (ep_table->structure_table_length == 0) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->structure_table_address, addr); + ACPI_READ_FIELD(data->qts, ep_table->number_of_structures, addr); + if (ep_table->number_of_structures == 0) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->smbios_bcd_revision, addr); + if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) || + acpi_calc_checksum((uint8_t *)ep_table + 0x10, + sizeof *ep_table - 0x10)) { + return false; + } + return true; +} + +static void test_smbios_entry_point(test_data *data) +{ + uint32_t off; + + /* find smbios entry point structure */ + for (off = 0xf0000; off < 0x100000; off += 0x10) { + uint8_t sig[] = "_SM_"; + int i; + + for (i = 0; i < sizeof sig - 1; ++i) { + sig[i] = qtest_readb(data->qts, off + i); + } + + if (!memcmp(sig, "_SM_", sizeof sig)) { + /* signature match, but is this a valid entry point? */ + data->smbios_ep_addr = off; + if (smbios_ep_table_ok(data)) { + break; + } + } + } + + g_assert_cmphex(off, <, 0x100000); +} + +static inline bool smbios_single_instance(uint8_t type) +{ + switch (type) { + case 0: + case 1: + case 2: + case 3: + case 16: + case 32: + case 127: + return true; + default: + return false; + } +} + +static void test_smbios_structs(test_data *data) +{ + DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 }; + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = le32_to_cpu(ep_table->structure_table_address); + int i, len, max_len = 0; + uint8_t type, prv, crt; + + /* walk the smbios tables */ + for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) { + + /* grab type and formatted area length from struct header */ + type = qtest_readb(data->qts, addr); + g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE); + len = qtest_readb(data->qts, addr + 1); + + /* single-instance structs must not have been encountered before */ + if (smbios_single_instance(type)) { + g_assert(!test_bit(type, struct_bitmap)); + } + set_bit(type, struct_bitmap); + + /* seek to end of unformatted string area of this struct ("\0\0") */ + prv = crt = 1; + while (prv || crt) { + prv = crt; + crt = qtest_readb(data->qts, addr + len); + len++; + } + + /* keep track of max. struct size */ + if (max_len < len) { + max_len = len; + g_assert_cmpuint(max_len, <=, ep_table->max_structure_size); + } + + /* start of next structure */ + addr += len; + } + + /* total table length and max struct size must match entry point values */ + g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==, + addr - le32_to_cpu(ep_table->structure_table_address)); + g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len); + + /* required struct types must all be present */ + for (i = 0; i < data->required_struct_types_len; i++) { + g_assert(test_bit(data->required_struct_types[i], struct_bitmap)); + } +} + +static void test_acpi_one(const char *params, test_data *data) +{ + char *args; + + /* Disable kernel irqchip to be able to override apic irq0. */ + args = g_strdup_printf("-machine %s,accel=%s,kernel-irqchip=off " + "-net none -display none %s " + "-drive id=hd0,if=none,file=%s,format=raw " + "-device ide-hd,drive=hd0 ", + data->machine, "kvm:tcg", + params ? params : "", disk); + + data->qts = qtest_init(args); + + boot_sector_test(data->qts); + + data->tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + test_acpi_rsdp_address(data); + test_acpi_rsdp_table(data); + test_acpi_rsdt_table(data); + fadt_fetch_facs_and_dsdt_ptrs(data); + test_acpi_facs_table(data); + test_acpi_dsdt_table(data); + fetch_rsdt_referenced_tables(data); + + sanitize_fadt_ptrs(data); + + if (iasl) { + if (getenv(ACPI_REBUILD_EXPECTED_AML)) { + dump_aml_files(data, true); + } else { + test_acpi_asl(data); + } + } + + test_smbios_entry_point(data); + test_smbios_structs(data); + + assert(!global_qtest); + qtest_quit(data->qts); + g_free(args); +} + +static uint8_t base_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 127 +}; + +static void test_acpi_piix4_tcg(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_mmio64(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".mmio64", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types) + }; + + test_acpi_one("-m 128M,slots=1,maxmem=2G " + "-device pci-testdev,membar=2G", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".cphp"; + test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".cphp"; + test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static uint8_t ipmi_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 38, 127 +}; + +static void test_acpi_q35_tcg_ipmi(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".ipmibt"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-bt,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_ipmi(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".ipmikcs"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-kcs,irq=0,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".numamem"; + test_acpi_one(" -numa node -numa node,mem=128", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".numamem"; + test_acpi_one(" -numa node -numa node,mem=128", &data); + free_test_data(&data); +} + +static void test_acpi_tcg_dimm_pxm(const char *machine) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = ".dimmpxm"; + test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu" + " -smp 4,sockets=4" + " -m 128M,slots=3,maxmem=1G" + " -numa node,mem=32M,nodeid=0" + " -numa node,mem=32M,nodeid=1" + " -numa node,mem=32M,nodeid=2" + " -numa node,mem=32M,nodeid=3" + " -numa cpu,node-id=0,socket-id=0" + " -numa cpu,node-id=1,socket-id=1" + " -numa cpu,node-id=2,socket-id=2" + " -numa cpu,node-id=3,socket-id=3" + " -object memory-backend-ram,id=ram0,size=128M" + " -object memory-backend-ram,id=nvm0,size=128M" + " -device pc-dimm,id=dimm0,memdev=ram0,node=1" + " -device nvdimm,id=dimm1,memdev=nvm0,node=2", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_Q35); +} + +static void test_acpi_piix4_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_PC); +} + +int main(int argc, char *argv[]) +{ + const char *arch = qtest_get_arch(); + int ret; + + ret = boot_sector_init(disk); + if(ret) + return ret; + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); + qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); + qtest_add_func("acpi/q35", test_acpi_q35_tcg); + qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); + qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); + qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); + qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp); + qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp); + qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp); + qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp); + qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem); + qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem); + qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm); + qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); + } + ret = g_test_run(); + boot_sector_cleanup(disk); + return ret; +} diff --git a/tests/data/acpi/diff-aml.sh b/tests/data/acpi/diff-aml.sh new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/disassemle-aml.py b/tests/data/acpi/disassemle-aml.py new file mode 100644 index 0000000000..0398fada63 --- /dev/null +++ b/tests/data/acpi/disassemle-aml.py @@ -0,0 +1,21 @@ +#!/usr/bin/python + +import os, re +root = "tests/data/acpi" +for machine in os.listdir(root): + machine_root = os.path.join(root, machine) + if not os.path.isdir(machine_root): + continue + files = os.listdir(machine_root): + for file in files: + if file.endswith(".dsl"): + continue + extension_prefix = "^[^.]*\." + if re.match(extension_prefix, file): + variant = re.sub(extension_prefix, "", file) + + +for dirpath, dirnames, filenames in os.walk("tests/data/acpi"): + for file in files: + if file.endswith(".txt"): + print(os.path.join(root, file)) diff --git a/tests/data/acpi/microvm/APIC.dsl b/tests/data/acpi/microvm/APIC.dsl new file mode 100644 index 0000000000..02f56dce43 --- /dev/null +++ b/tests/data/acpi/microvm/APIC.dsl @@ -0,0 +1,56 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/microvm/APIC, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000046 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D7 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 04 [Local APIC NMI] +[041h 0065 1] Length : 06 +[042h 0066 1] Processor ID : FF +[043h 0067 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[045h 0069 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 70 (0x46) + + 0000: 41 50 49 43 46 00 00 00 01 D7 42 4F 43 48 53 20 // APICF.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 04 06 FF 00 00 01 // ...... diff --git a/tests/data/acpi/microvm/DSDT.dsl b/tests/data/acpi/microvm/DSDT.dsl new file mode 100644 index 0000000000..fd53f08128 --- /dev/null +++ b/tests/data/acpi/microvm/DSDT.dsl @@ -0,0 +1,121 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/microvm/DSDT, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000016D (365) + * Revision 0x02 + * Checksum 0x62 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (_SB) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000009, + } + }) + OperationRegion (EREG, SystemMemory, 0xFEA00000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFEB00E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000017, + } + }) + } + } + + Scope (\) + { + Name (_S5, Package (0x04) // _S5_: S5 System State + { + 0x05, + Zero, + Zero, + Zero + }) + } +} + diff --git a/tests/data/acpi/microvm/FACP.dsl b/tests/data/acpi/microvm/FACP.dsl new file mode 100644 index 0000000000..4cf780caec --- /dev/null +++ b/tests/data/acpi/microvm/FACP.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/microvm/FACP, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : 7E +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100400 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 00000000FEA00202 + +[080h 0128 1] Value to cause reset : 42 +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 08 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 00000000FEA00200 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 08 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 00000000FEA00201 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 7E 42 4F 43 48 53 20 // FACP.....~BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 04 10 00 00 08 00 00 02 02 A0 FE 00 00 00 00 // ................ + 0080: 42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // B............... + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 08 00 00 00 02 A0 FE 00 00 00 00 // ................ + 0100: 00 08 00 00 01 02 A0 FE 00 00 00 00 // ............ diff --git a/tests/data/acpi/pc/APIC.acpihmat.dsl b/tests/data/acpi/pc/APIC.acpihmat.dsl new file mode 100644 index 0000000000..15155cac55 --- /dev/null +++ b/tests/data/acpi/pc/APIC.acpihmat.dsl @@ -0,0 +1,112 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000080 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : DA +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 01 [I/O APIC] +[03Dh 0061 1] Length : 0C +[03Eh 0062 1] I/O Apic ID : 00 +[03Fh 0063 1] Reserved : 00 +[040h 0064 4] Address : FEC00000 +[044h 0068 4] Interrupt : 00000000 + +[048h 0072 1] Subtable Type : 02 [Interrupt Source Override] +[049h 0073 1] Length : 0A +[04Ah 0074 1] Bus : 00 +[04Bh 0075 1] Source : 00 +[04Ch 0076 4] Interrupt : 00000002 +[050h 0080 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[052h 0082 1] Subtable Type : 02 [Interrupt Source Override] +[053h 0083 1] Length : 0A +[054h 0084 1] Bus : 00 +[055h 0085 1] Source : 05 +[056h 0086 4] Interrupt : 00000005 +[05Ah 0090 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Ch 0092 1] Subtable Type : 02 [Interrupt Source Override] +[05Dh 0093 1] Length : 0A +[05Eh 0094 1] Bus : 00 +[05Fh 0095 1] Source : 09 +[060h 0096 4] Interrupt : 00000009 +[064h 0100 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[066h 0102 1] Subtable Type : 02 [Interrupt Source Override] +[067h 0103 1] Length : 0A +[068h 0104 1] Bus : 00 +[069h 0105 1] Source : 0A +[06Ah 0106 4] Interrupt : 0000000A +[06Eh 0110 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[070h 0112 1] Subtable Type : 02 [Interrupt Source Override] +[071h 0113 1] Length : 0A +[072h 0114 1] Bus : 00 +[073h 0115 1] Source : 0B +[074h 0116 4] Interrupt : 0000000B +[078h 0120 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ah 0122 1] Subtable Type : 04 [Local APIC NMI] +[07Bh 0123 1] Length : 06 +[07Ch 0124 1] Processor ID : FF +[07Dh 0125 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[07Fh 0127 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 128 (0x80) + + 0000: 41 50 49 43 80 00 00 00 01 DA 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 00 00 // ................ + 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0050: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0060: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0070: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.bridge b/tests/data/acpi/pc/APIC.bridge new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/APIC.bridge.dsl b/tests/data/acpi/pc/APIC.bridge.dsl new file mode 100644 index 0000000000..2828370063 --- /dev/null +++ b/tests/data/acpi/pc/APIC.bridge.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.cphp.dsl b/tests/data/acpi/pc/APIC.cphp.dsl new file mode 100644 index 0000000000..b4b043229a --- /dev/null +++ b/tests/data/acpi/pc/APIC.cphp.dsl @@ -0,0 +1,146 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 7B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 04 +[048h 0072 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC] +[04Dh 0077 1] Length : 08 +[04Eh 0078 1] Processor ID : 04 +[04Fh 0079 1] Local Apic ID : 05 +[050h 0080 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[054h 0084 1] Subtable Type : 00 [Processor Local APIC] +[055h 0085 1] Length : 08 +[056h 0086 1] Processor ID : 05 +[057h 0087 1] Local Apic ID : 06 +[058h 0088 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[05Ch 0092 1] Subtable Type : 01 [I/O APIC] +[05Dh 0093 1] Length : 0C +[05Eh 0094 1] I/O Apic ID : 00 +[05Fh 0095 1] Reserved : 00 +[060h 0096 4] Address : FEC00000 +[064h 0100 4] Interrupt : 00000000 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 00 +[06Ch 0108 4] Interrupt : 00000002 +[070h 0112 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[072h 0114 1] Subtable Type : 02 [Interrupt Source Override] +[073h 0115 1] Length : 0A +[074h 0116 1] Bus : 00 +[075h 0117 1] Source : 05 +[076h 0118 4] Interrupt : 00000005 +[07Ah 0122 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override] +[07Dh 0125 1] Length : 0A +[07Eh 0126 1] Bus : 00 +[07Fh 0127 1] Source : 09 +[080h 0128 4] Interrupt : 00000009 +[084h 0132 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[086h 0134 1] Subtable Type : 02 [Interrupt Source Override] +[087h 0135 1] Length : 0A +[088h 0136 1] Bus : 00 +[089h 0137 1] Source : 0A +[08Ah 0138 4] Interrupt : 0000000A +[08Eh 0142 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[090h 0144 1] Subtable Type : 02 [Interrupt Source Override] +[091h 0145 1] Length : 0A +[092h 0146 1] Bus : 00 +[093h 0147 1] Source : 0B +[094h 0148 4] Interrupt : 0000000B +[098h 0152 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI] +[09Bh 0155 1] Length : 06 +[09Ch 0156 1] Processor ID : FF +[09Dh 0157 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[09Fh 0159 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 160 (0xA0) + + 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................ + 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................ + 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.dimmpxm.dsl b/tests/data/acpi/pc/APIC.dimmpxm.dsl new file mode 100644 index 0000000000..adabdcc603 --- /dev/null +++ b/tests/data/acpi/pc/APIC.dimmpxm.dsl @@ -0,0 +1,129 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000090 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : AE +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 03 +[048h 0072 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 01 [I/O APIC] +[04Dh 0077 1] Length : 0C +[04Eh 0078 1] I/O Apic ID : 00 +[04Fh 0079 1] Reserved : 00 +[050h 0080 4] Address : FEC00000 +[054h 0084 4] Interrupt : 00000000 + +[058h 0088 1] Subtable Type : 02 [Interrupt Source Override] +[059h 0089 1] Length : 0A +[05Ah 0090 1] Bus : 00 +[05Bh 0091 1] Source : 00 +[05Ch 0092 4] Interrupt : 00000002 +[060h 0096 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[062h 0098 1] Subtable Type : 02 [Interrupt Source Override] +[063h 0099 1] Length : 0A +[064h 0100 1] Bus : 00 +[065h 0101 1] Source : 05 +[066h 0102 4] Interrupt : 00000005 +[06Ah 0106 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override] +[06Dh 0109 1] Length : 0A +[06Eh 0110 1] Bus : 00 +[06Fh 0111 1] Source : 09 +[070h 0112 4] Interrupt : 00000009 +[074h 0116 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[076h 0118 1] Subtable Type : 02 [Interrupt Source Override] +[077h 0119 1] Length : 0A +[078h 0120 1] Bus : 00 +[079h 0121 1] Source : 0A +[07Ah 0122 4] Interrupt : 0000000A +[07Eh 0126 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[080h 0128 1] Subtable Type : 02 [Interrupt Source Override] +[081h 0129 1] Length : 0A +[082h 0130 1] Bus : 00 +[083h 0131 1] Source : 0B +[084h 0132 4] Interrupt : 0000000B +[088h 0136 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI] +[08Bh 0139 1] Length : 06 +[08Ch 0140 1] Processor ID : FF +[08Dh 0141 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[08Fh 0143 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 144 (0x90) + + 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................ + 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.dsl b/tests/data/acpi/pc/APIC.dsl new file mode 100644 index 0000000000..d9516fc1f2 --- /dev/null +++ b/tests/data/acpi/pc/APIC.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.hpbridge b/tests/data/acpi/pc/APIC.hpbridge new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/APIC.ipmikcs b/tests/data/acpi/pc/APIC.ipmikcs new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/APIC.ipmikcs.dsl b/tests/data/acpi/pc/APIC.ipmikcs.dsl new file mode 100644 index 0000000000..28198bed68 --- /dev/null +++ b/tests/data/acpi/pc/APIC.ipmikcs.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.memhp b/tests/data/acpi/pc/APIC.memhp new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/APIC.memhp.dsl b/tests/data/acpi/pc/APIC.memhp.dsl new file mode 100644 index 0000000000..b8449c0bde --- /dev/null +++ b/tests/data/acpi/pc/APIC.memhp.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.numamem b/tests/data/acpi/pc/APIC.numamem new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/APIC.numamem.dsl b/tests/data/acpi/pc/APIC.numamem.dsl new file mode 100644 index 0000000000..d75e4283d1 --- /dev/null +++ b/tests/data/acpi/pc/APIC.numamem.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.roothp b/tests/data/acpi/pc/APIC.roothp new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/pc/DSDT.acpihmat.dsl b/tests/data/acpi/pc/DSDT.acpihmat.dsl new file mode 100644 index 0000000000..b2a4b1bd7f --- /dev/null +++ b/tests/data/acpi/pc/DSDT.acpihmat.dsl @@ -0,0 +1,1619 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001872 (6258) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x8E + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x02) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000001C0000000, // Range Minimum + 0x000000023FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.bridge.dsl b/tests/data/acpi/pc/DSDT.bridge.dsl new file mode 100644 index 0000000000..3311b57ecb --- /dev/null +++ b/tests/data/acpi/pc/DSDT.bridge.dsl @@ -0,0 +1,1800 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.bridge, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001A89 (6793) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x09 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + Name (BSEL, One) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S08) + { + Name (_SUN, One) // _SUN: Slot User Number + Name (_ADR, 0x00010000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S10) + { + Name (_SUN, 0x02) // _SUN: Slot User Number + Name (_ADR, 0x00020000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + + If ((Arg0 & 0x02)) + { + Notify (S08, Arg1) + } + + If ((Arg0 & 0x04)) + { + Notify (S10, Arg1) + } + + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = One + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + ^S18.PCNT () + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.cphp.dsl b/tests/data/acpi/pc/DSDT.cphp.dsl new file mode 100644 index 0000000000..22ed37d7dc --- /dev/null +++ b/tests/data/acpi/pc/DSDT.cphp.dsl @@ -0,0 +1,1466 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.cphp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001515 (5397) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x39 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + + If ((Arg0 == 0x04)) + { + Notify (C004, Arg1) + } + + If ((Arg0 == 0x05)) + { + Notify (C005, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C004, 0x04, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x04)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x04) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x04, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C005, 0x05, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x05)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x05) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x05, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.dimmpxm.dsl b/tests/data/acpi/pc/DSDT.dimmpxm.dsl new file mode 100644 index 0000000000..798056147b --- /dev/null +++ b/tests/data/acpi/pc/DSDT.dimmpxm.dsl @@ -0,0 +1,1719 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000019BB (6587) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x21 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x02) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x03) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + + Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x000000027FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.dsl b/tests/data/acpi/pc/DSDT.dsl new file mode 100644 index 0000000000..da2b413efc --- /dev/null +++ b/tests/data/acpi/pc/DSDT.dsl @@ -0,0 +1,1407 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.roothp, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001488 (5256) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xF2 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Name (CNEW, Package (0xFF){}) + Local3 = Zero + Local4 = One + While ((Local4 == One)) + { + Local4 = Zero + Local0 = One + Local1 = Zero + While (((Local0 == One) && (Local3 < One))) + { + Local0 = Zero + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CDAT < Local3)) + { + Break + } + + If ((Local1 == 0xFF)) + { + Local4 = One + Break + } + + Local3 = \_SB.PCI0.PRES.CDAT + If ((\_SB.PCI0.PRES.CINS == One)) + { + CNEW [Local1] = Local3 + Local1++ + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + + Local3++ + } + + Local2 = Zero + While ((Local2 < Local1)) + { + Local3 = DerefOf (CNEW [Local2]) + CTFY (Local3, One) + Debug = Local3 + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CINS = One + Local2++ + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S08) + { + Name (_SUN, One) // _SUN: Slot User Number + Name (_ADR, 0x00010000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S10) + { + Name (_SUN, 0x02) // _SUN: Slot User Number + Name (_ADR, 0x00020000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + + If ((Arg0 & 0x02)) + { + Notify (S08, Arg1) + } + + If ((Arg0 & 0x04)) + { + Notify (S10, Arg1) + } + + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + + Method (PCNT, 0, NotSerialized) + { + ^S18.PCNT () + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.hpbridge b/tests/data/acpi/pc/DSDT.hpbridge index b0751398541bdf88ce405be9742aeba0b375dbc3..56032bcf1ba4e251f16c9028429826090531efdd 100644 GIT binary patch delta 323 zcwU>YHdmd?CD+d@E<%%27z-Fu3K$a#7!nux@JyJTz&JG-D3nl;9HY+?AM6w#;OuD-5ab%{ z9PH{-z<@63?CY{Xd@8!Ai(^Rg(gmE86S@8atyx+Cldnfsus~%px;{_8V8(*v4v-@g z8A=m@&RS@`z!XDSkZ%~HbBJ4HG8c0JBNj=ZzS86ZhNMNVEK`#b3!1?OCNU&CbAvPi YZHP83NS>_2p~?!hurz72E$1Un09SQks{jB1 delta 193 zcwU>UK3|Q?CDG5)3}Gx_#G)E# h?m};t1s*JuZ8#-$v1sFB#?%+&8wS+3c{k@HP5_n-HcS8j diff --git a/tests/data/acpi/pc/DSDT.ipmikcs.dsl b/tests/data/acpi/pc/DSDT.ipmikcs.dsl new file mode 100644 index 0000000000..2e4b524ab8 --- /dev/null +++ b/tests/data/acpi/pc/DSDT.ipmikcs.dsl @@ -0,0 +1,1337 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000138E (5006) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x54 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (MI1) + { + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, "ipmi_kcs") // _STR: Description String + Name (_UID, One) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, // Range Minimum + 0x0CA3, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + }) + Name (_IFT, One) // _IFT: IPMI Interface Type + Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision + } + + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.memhp.dsl b/tests/data/acpi/pc/DSDT.memhp.dsl new file mode 100644 index 0000000000..299315051e --- /dev/null +++ b/tests/data/acpi/pc/DSDT.memhp.dsl @@ -0,0 +1,1625 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001895 (6293) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xB2 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x000000027FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.numamem.dsl b/tests/data/acpi/pc/DSDT.numamem.dsl new file mode 100644 index 0000000000..3d08447f1e --- /dev/null +++ b/tests/data/acpi/pc/DSDT.numamem.dsl @@ -0,0 +1,1321 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000134C (4940) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x6A + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.roothp b/tests/data/acpi/pc/DSDT.roothp index 886a5e6952f6f034bdd80d44d43de5975a1a4b0f..18caa0765fc10adb29e01717390ead6c63cd0f3c 100644 GIT binary patch delta 323 zcwXz$=+NYH33dtT5Mf|o{Irp43mcP{-Q)votC@U_C+D*NWpWdnoWmhg&*ALn8ZN~2 zzkngRfH7r}i_qj0#sY?v0>*>_hQviaJQF4-FiuSd3MCXI$LO=f2Rp?FIC~ld1i1z~ z2fO+dFrW)M`?@R;pNcN(;uw;=bOGn&M6UlpYnB$kp8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67p8$^tS4I$3~ cWItFB6=z~#VFA+r`Tz67*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.bridge.dsl b/tests/data/acpi/q35/APIC.bridge.dsl new file mode 100644 index 0000000000..2489067401 --- /dev/null +++ b/tests/data/acpi/q35/APIC.bridge.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.cphp.dsl b/tests/data/acpi/q35/APIC.cphp.dsl new file mode 100644 index 0000000000..be8daf5f80 --- /dev/null +++ b/tests/data/acpi/q35/APIC.cphp.dsl @@ -0,0 +1,146 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 7B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 04 +[048h 0072 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC] +[04Dh 0077 1] Length : 08 +[04Eh 0078 1] Processor ID : 04 +[04Fh 0079 1] Local Apic ID : 05 +[050h 0080 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[054h 0084 1] Subtable Type : 00 [Processor Local APIC] +[055h 0085 1] Length : 08 +[056h 0086 1] Processor ID : 05 +[057h 0087 1] Local Apic ID : 06 +[058h 0088 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[05Ch 0092 1] Subtable Type : 01 [I/O APIC] +[05Dh 0093 1] Length : 0C +[05Eh 0094 1] I/O Apic ID : 00 +[05Fh 0095 1] Reserved : 00 +[060h 0096 4] Address : FEC00000 +[064h 0100 4] Interrupt : 00000000 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 00 +[06Ch 0108 4] Interrupt : 00000002 +[070h 0112 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[072h 0114 1] Subtable Type : 02 [Interrupt Source Override] +[073h 0115 1] Length : 0A +[074h 0116 1] Bus : 00 +[075h 0117 1] Source : 05 +[076h 0118 4] Interrupt : 00000005 +[07Ah 0122 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override] +[07Dh 0125 1] Length : 0A +[07Eh 0126 1] Bus : 00 +[07Fh 0127 1] Source : 09 +[080h 0128 4] Interrupt : 00000009 +[084h 0132 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[086h 0134 1] Subtable Type : 02 [Interrupt Source Override] +[087h 0135 1] Length : 0A +[088h 0136 1] Bus : 00 +[089h 0137 1] Source : 0A +[08Ah 0138 4] Interrupt : 0000000A +[08Eh 0142 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[090h 0144 1] Subtable Type : 02 [Interrupt Source Override] +[091h 0145 1] Length : 0A +[092h 0146 1] Bus : 00 +[093h 0147 1] Source : 0B +[094h 0148 4] Interrupt : 0000000B +[098h 0152 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI] +[09Bh 0155 1] Length : 06 +[09Ch 0156 1] Processor ID : FF +[09Dh 0157 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[09Fh 0159 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 160 (0xA0) + + 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................ + 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................ + 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/q35/APIC.dimmpxm.dsl b/tests/data/acpi/q35/APIC.dimmpxm.dsl new file mode 100644 index 0000000000..798ab91bed --- /dev/null +++ b/tests/data/acpi/q35/APIC.dimmpxm.dsl @@ -0,0 +1,129 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000090 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : AE +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 03 +[048h 0072 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 01 [I/O APIC] +[04Dh 0077 1] Length : 0C +[04Eh 0078 1] I/O Apic ID : 00 +[04Fh 0079 1] Reserved : 00 +[050h 0080 4] Address : FEC00000 +[054h 0084 4] Interrupt : 00000000 + +[058h 0088 1] Subtable Type : 02 [Interrupt Source Override] +[059h 0089 1] Length : 0A +[05Ah 0090 1] Bus : 00 +[05Bh 0091 1] Source : 00 +[05Ch 0092 4] Interrupt : 00000002 +[060h 0096 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[062h 0098 1] Subtable Type : 02 [Interrupt Source Override] +[063h 0099 1] Length : 0A +[064h 0100 1] Bus : 00 +[065h 0101 1] Source : 05 +[066h 0102 4] Interrupt : 00000005 +[06Ah 0106 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override] +[06Dh 0109 1] Length : 0A +[06Eh 0110 1] Bus : 00 +[06Fh 0111 1] Source : 09 +[070h 0112 4] Interrupt : 00000009 +[074h 0116 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[076h 0118 1] Subtable Type : 02 [Interrupt Source Override] +[077h 0119 1] Length : 0A +[078h 0120 1] Bus : 00 +[079h 0121 1] Source : 0A +[07Ah 0122 4] Interrupt : 0000000A +[07Eh 0126 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[080h 0128 1] Subtable Type : 02 [Interrupt Source Override] +[081h 0129 1] Length : 0A +[082h 0130 1] Bus : 00 +[083h 0131 1] Source : 0B +[084h 0132 4] Interrupt : 0000000B +[088h 0136 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI] +[08Bh 0139 1] Length : 06 +[08Ch 0140 1] Processor ID : FF +[08Dh 0141 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[08Fh 0143 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 144 (0x90) + + 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................ + 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/q35/APIC.dsl b/tests/data/acpi/q35/APIC.dsl new file mode 100644 index 0000000000..77d2d2c0a5 --- /dev/null +++ b/tests/data/acpi/q35/APIC.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.ipmibt b/tests/data/acpi/q35/APIC.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.ipmibt.dsl b/tests/data/acpi/q35/APIC.ipmibt.dsl new file mode 100644 index 0000000000..127e21e2fe --- /dev/null +++ b/tests/data/acpi/q35/APIC.ipmibt.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.memhp b/tests/data/acpi/q35/APIC.memhp new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.memhp.dsl b/tests/data/acpi/q35/APIC.memhp.dsl new file mode 100644 index 0000000000..1c0cb1dad1 --- /dev/null +++ b/tests/data/acpi/q35/APIC.memhp.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.mmio64 b/tests/data/acpi/q35/APIC.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.mmio64.dsl b/tests/data/acpi/q35/APIC.mmio64.dsl new file mode 100644 index 0000000000..9a3df90766 --- /dev/null +++ b/tests/data/acpi/q35/APIC.mmio64.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.numamem b/tests/data/acpi/q35/APIC.numamem new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.numamem.dsl b/tests/data/acpi/q35/APIC.numamem.dsl new file mode 100644 index 0000000000..f4c5480fd6 --- /dev/null +++ b/tests/data/acpi/q35/APIC.numamem.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.tis b/tests/data/acpi/q35/APIC.tis new file mode 100644 index 0000000000000000000000000000000000000000..84509e0ae4cabeb5ead3e42a4edfa50abddbc17d GIT binary patch literal 120 zcwTc1@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2U5!e;vDz~BAK{= fm;uUSWd+i_AQmSljK#$TV{vnXSuAY-fkprTJtz$U literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/APIC.tis.dsl b/tests/data/acpi/q35/APIC.tis.dsl new file mode 100644 index 0000000000..ca2373818e --- /dev/null +++ b/tests/data/acpi/q35/APIC.tis.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index d6c26940b1a68d4184f6f2335924099aa28b130a..e7414e78563372fca4d2aab9d16c58c0ff8468f4 100644 GIT binary patch delta 33 ocwYNs^TmeCCD-hQE4NWiX5jKOH6#QQ@nuPWD7Z40H)^%$^ZZW delta 42 xcwYNr^T&qECD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x02) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000001C0000000, // Range Minimum + 0x00000009BFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.bridge b/tests/data/acpi/q35/DSDT.bridge index 0f6c9c68c81cddd2126eea8a7c336b8667202223..118476ff6101e11d6b1f2d3399241d7fd1a6f634 100644 GIT binary patch delta 33 ocwXzZZL{Ta33dr-lVf0D+`W-YMUK;hH6}jTDPF)~vbmf;0GQ4QumAu6 delta 41 wcwTF>?X~4{33dtTm1AIF4ByD5BFE{^8WSJv6ffXD*<8+_U4$*b*)N0v0NR)dw*UYD diff --git a/tests/data/acpi/q35/DSDT.bridge.dsl b/tests/data/acpi/q35/DSDT.bridge.dsl new file mode 100644 index 0000000000..51fbeb729d --- /dev/null +++ b/tests/data/acpi/q35/DSDT.bridge.dsl @@ -0,0 +1,3141 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.bridge, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001E0F (7695) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x4B + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.cphp b/tests/data/acpi/q35/DSDT.cphp index d7bedee7ff638f11b3bb84ef960364b409a49cce..69c5edf620529e995461ccba63b76a083f25b2b6 100644 GIT binary patch delta 33 ocwRf>aKwSjCD delta 42 xcwRf=aK?elCD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + + If ((Arg0 == 0x04)) + { + Notify (C004, Arg1) + } + + If ((Arg0 == 0x05)) + { + Notify (C005, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C004, 0x04, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x04)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x04) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x04, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C005, 0x05, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x05)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x05) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x05, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.dimmpxm b/tests/data/acpi/q35/DSDT.dimmpxm index 13e80ae2e5c7606a7260d4cb3ab776488d0697d6..af41acba6e0117191ad8495a30ded7b0acc4d2ca 100644 GIT binary patch delta 33 pcwYPD`O1^aCD)(0sz0?3UmMf delta 42 ycwT$u`N@;ZCD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x02) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x03) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.dsl b/tests/data/acpi/q35/DSDT.dsl new file mode 100644 index 0000000000..5adfe001c7 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.dsl @@ -0,0 +1,3351 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.tis, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000020D2 (8402) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xF4 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Name (CNEW, Package (0xFF){}) + Local3 = Zero + Local4 = One + While ((Local4 == One)) + { + Local4 = Zero + Local0 = One + Local1 = Zero + While (((Local0 == One) && (Local3 < One))) + { + Local0 = Zero + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CDAT < Local3)) + { + Break + } + + If ((Local1 == 0xFF)) + { + Local4 = One + Break + } + + Local3 = \_SB.PCI0.PRES.CDAT + If ((\_SB.PCI0.PRES.CINS == One)) + { + CNEW [Local1] = Local3 + Local1++ + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + + Local3++ + } + + Local2 = Zero + While ((Local2 < Local1)) + { + Local3 = DerefOf (CNEW [Local2]) + CTFY (Local3, One) + Debug = Local3 + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CINS = One + Local2++ + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A) + Field (TPP2, AnyAcc, NoLock, Preserve) + { + PPIN, 8, + PPIP, 32, + PPRP, 32, + PPRQ, 32, + PPRM, 32, + LPPR, 32 + } + + OperationRegion (TPP3, SystemMemory, 0xFED4515A, One) + Field (TPP3, ByteAcc, NoLock, Preserve) + { + MOVV, 8 + } + + Method (TPFN, 1, Serialized) + { + If ((Arg0 >= 0x0100)) + { + Return (Zero) + } + + OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One) + Field (TPP1, ByteAcc, NoLock, Preserve) + { + TPPF, 8 + } + + Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */ + } + + Name (TPM2, Package (0x02) + { + Zero, + Zero + }) + Name (TPM3, Package (0x03) + { + Zero, + Zero, + Zero + }) + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + + If ((Arg2 == One)) + { + Return ("1.3") + } + + If ((Arg2 == 0x02)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + PPRQ = Local0 + PPRM = Zero + Return (Zero) + } + + If ((Arg2 == 0x03)) + { + If ((Arg1 == One)) + { + TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */ + } + + If ((Arg1 == 0x02)) + { + TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + } + + If ((Arg2 == 0x04)) + { + Return (0x02) + } + + If ((Arg2 == 0x05)) + { + TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */ + TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + + If ((Arg2 == 0x06)) + { + Return (0x03) + } + + If ((Arg2 == 0x07)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + If (((Local1 & 0x07) == 0x02)) + { + Return (0x03) + } + + If ((Arg1 == One)) + { + PPRQ = Local0 + PPRM = Zero + } + + If ((Arg1 == 0x02)) + { + PPRQ = Local0 + PPRM = DerefOf (Arg3 [One]) + } + + Return (Zero) + } + + If ((Arg2 == 0x08)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + Return ((Local1 & 0x07)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + + If ((Arg2 == One)) + { + Local0 = DerefOf (Arg3 [Zero]) + MOVV = Local0 + Return (Zero) + } + } + } + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipmibt index 9a1b635dab776fb25e378a00e6ca0cadf9902c25..a650c3041ab9d6688eda843a6a2ab418e1a7ce9b 100644 GIT binary patch delta 33 ocwRehyWf_}CD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (MI1) + { + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, "ipmi_bt") // _STR: Description String + Name (_UID, One) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x00E4, // Range Minimum + 0x00E6, // Range Maximum + 0x01, // Alignment + 0x03, // Length + ) + IRQNoFlags () + {5} + }) + Name (_IFT, 0x03) // _IFT: IPMI Interface Type + Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision + } + + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.memhp b/tests/data/acpi/q35/DSDT.memhp index 55ce4e2293624c2c0725c3bbaaa7ec29acfccfc9..85598ca3f68f437e8d5048e2cb9815f20b332152 100644 GIT binary patch delta 33 ocwRg0e%PJMCD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.mmio64 b/tests/data/acpi/q35/DSDT.mmio64 index 99b7b2ae4ba36b8ca7901626c1561d29100087d2..092fdc32628f5a145b510c2a46de8b02222b1951 100644 GIT binary patch delta 33 pcwT$vdf%1HCD>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, One) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.numamem b/tests/data/acpi/q35/DSDT.numamem index 2b2433cc13ec3110abbc8440a0b1ad8c487edb6c..899946255b9111e077e06c5f78be860e863911b9 100644 GIT binary patch delta 33 ocwTF={bj@D66_LECC9+PcxEG)mK>)WOH6#QQ@nuPWIH)q0Hvo16951J delta 42 xcwYNu(`3u#66_MvB*(zOn7ENkOODHrB_=-DDPF*hWwNcDExQO?fU{o+0|4^g3K{?a diff --git a/tests/data/acpi/q35/DSDT.numamem.dsl b/tests/data/acpi/q35/DSDT.numamem.dsl new file mode 100644 index 0000000000..e76de462f0 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.numamem.dsl @@ -0,0 +1,3138 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001E04 (7684) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x55 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.tis b/tests/data/acpi/q35/DSDT.tis index dd06ee4c348930b0684827ca05747b4f65dbd6b2..08802fbd12eae6ad99f03a8db9a0bc7f95e77cb4 100644 GIT binary patch delta 38 ucwW2dc*&8=CDDs0RTDD B46OhF diff --git a/tests/data/acpi/q35/DSDT.tis.dsl b/tests/data/acpi/q35/DSDT.tis.dsl new file mode 100644 index 0000000000..a43e36bfe3 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.tis.dsl @@ -0,0 +1,3321 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.tis, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000205B (8283) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x84 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A) + Field (TPP2, AnyAcc, NoLock, Preserve) + { + PPIN, 8, + PPIP, 32, + PPRP, 32, + PPRQ, 32, + PPRM, 32, + LPPR, 32 + } + + OperationRegion (TPP3, SystemMemory, 0xFED4515A, One) + Field (TPP3, ByteAcc, NoLock, Preserve) + { + MOVV, 8 + } + + Method (TPFN, 1, Serialized) + { + If ((Arg0 >= 0x0100)) + { + Return (Zero) + } + + OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One) + Field (TPP1, ByteAcc, NoLock, Preserve) + { + TPPF, 8 + } + + Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */ + } + + Name (TPM2, Package (0x02) + { + Zero, + Zero + }) + Name (TPM3, Package (0x03) + { + Zero, + Zero, + Zero + }) + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + + If ((Arg2 == One)) + { + Return ("1.3") + } + + If ((Arg2 == 0x02)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + PPRQ = Local0 + PPRM = Zero + Return (Zero) + } + + If ((Arg2 == 0x03)) + { + If ((Arg1 == One)) + { + TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */ + } + + If ((Arg1 == 0x02)) + { + TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + } + + If ((Arg2 == 0x04)) + { + Return (0x02) + } + + If ((Arg2 == 0x05)) + { + TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */ + TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + + If ((Arg2 == 0x06)) + { + Return (0x03) + } + + If ((Arg2 == 0x07)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + If (((Local1 & 0x07) == 0x02)) + { + Return (0x03) + } + + If ((Arg1 == One)) + { + PPRQ = Local0 + PPRM = Zero + } + + If ((Arg1 == 0x02)) + { + PPRQ = Local0 + PPRM = DerefOf (Arg3 [One]) + } + + Return (Zero) + } + + If ((Arg2 == 0x08)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + Return ((Local1 & 0x07)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + + If ((Arg2 == One)) + { + Local0 = DerefOf (Arg3 [Zero]) + MOVV = Local0 + Return (Zero) + } + } + } + } + } + } +} + diff --git a/tests/data/acpi/q35/FACP.acpihmat b/tests/data/acpi/q35/FACP.acpihmat new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.acpihmat.dsl b/tests/data/acpi/q35/FACP.acpihmat.dsl new file mode 100644 index 0000000000..29466227a1 --- /dev/null +++ b/tests/data/acpi/q35/FACP.acpihmat.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.bridge b/tests/data/acpi/q35/FACP.bridge new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.bridge.dsl b/tests/data/acpi/q35/FACP.bridge.dsl new file mode 100644 index 0000000000..2416f4391a --- /dev/null +++ b/tests/data/acpi/q35/FACP.bridge.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.cphp b/tests/data/acpi/q35/FACP.cphp new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.cphp.dsl b/tests/data/acpi/q35/FACP.cphp.dsl new file mode 100644 index 0000000000..96ee322b53 --- /dev/null +++ b/tests/data/acpi/q35/FACP.cphp.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.dimmpxm b/tests/data/acpi/q35/FACP.dimmpxm new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.dimmpxm.dsl b/tests/data/acpi/q35/FACP.dimmpxm.dsl new file mode 100644 index 0000000000..14f7c181b8 --- /dev/null +++ b/tests/data/acpi/q35/FACP.dimmpxm.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.dsl b/tests/data/acpi/q35/FACP.dsl new file mode 100644 index 0000000000..1a8893b320 --- /dev/null +++ b/tests/data/acpi/q35/FACP.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.ipmibt b/tests/data/acpi/q35/FACP.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.ipmibt.dsl b/tests/data/acpi/q35/FACP.ipmibt.dsl new file mode 100644 index 0000000000..b6e56c5af2 --- /dev/null +++ b/tests/data/acpi/q35/FACP.ipmibt.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.memhp b/tests/data/acpi/q35/FACP.memhp new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.memhp.dsl b/tests/data/acpi/q35/FACP.memhp.dsl new file mode 100644 index 0000000000..2405fcdca8 --- /dev/null +++ b/tests/data/acpi/q35/FACP.memhp.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.mmio64 b/tests/data/acpi/q35/FACP.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.mmio64.dsl b/tests/data/acpi/q35/FACP.mmio64.dsl new file mode 100644 index 0000000000..9f51c42156 --- /dev/null +++ b/tests/data/acpi/q35/FACP.mmio64.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.numamem b/tests/data/acpi/q35/FACP.numamem new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.numamem.dsl b/tests/data/acpi/q35/FACP.numamem.dsl new file mode 100644 index 0000000000..a5854c1a69 --- /dev/null +++ b/tests/data/acpi/q35/FACP.numamem.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.tis b/tests/data/acpi/q35/FACP.tis new file mode 100644 index 0000000000000000000000000000000000000000..72c9d97902a4bbf14896023d9ba78e0899d6517b GIT binary patch literal 244 zcwTdJbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!iFCT1YP1`%UnL&$Rg z*$OamCI%J(ApM{JKR-;~2#A-q0L|fGVED-c5ra!20Y(J|xcMmJ0;u+31B?m~cYxUq I2=^cZ0OVi}0RR91 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACP.tis.dsl b/tests/data/acpi/q35/FACP.tis.dsl new file mode 100644 index 0000000000..22f6a34466 --- /dev/null +++ b/tests/data/acpi/q35/FACP.tis.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACS.acpihmat b/tests/data/acpi/q35/FACS.acpihmat new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.acpihmat.dsl b/tests/data/acpi/q35/FACS.acpihmat.dsl new file mode 100644 index 0000000000..0bd98653ce --- /dev/null +++ b/tests/data/acpi/q35/FACS.acpihmat.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.bridge b/tests/data/acpi/q35/FACS.bridge new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.bridge.dsl b/tests/data/acpi/q35/FACS.bridge.dsl new file mode 100644 index 0000000000..116dce1f2d --- /dev/null +++ b/tests/data/acpi/q35/FACS.bridge.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.cphp b/tests/data/acpi/q35/FACS.cphp new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.cphp.dsl b/tests/data/acpi/q35/FACS.cphp.dsl new file mode 100644 index 0000000000..580d502491 --- /dev/null +++ b/tests/data/acpi/q35/FACS.cphp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.dimmpxm b/tests/data/acpi/q35/FACS.dimmpxm new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.dimmpxm.dsl b/tests/data/acpi/q35/FACS.dimmpxm.dsl new file mode 100644 index 0000000000..4106387866 --- /dev/null +++ b/tests/data/acpi/q35/FACS.dimmpxm.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.dsl b/tests/data/acpi/q35/FACS.dsl new file mode 100644 index 0000000000..0595b4ddb9 --- /dev/null +++ b/tests/data/acpi/q35/FACS.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.ipmibt b/tests/data/acpi/q35/FACS.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.ipmibt.dsl b/tests/data/acpi/q35/FACS.ipmibt.dsl new file mode 100644 index 0000000000..8c019f3475 --- /dev/null +++ b/tests/data/acpi/q35/FACS.ipmibt.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.memhp b/tests/data/acpi/q35/FACS.memhp new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.memhp.dsl b/tests/data/acpi/q35/FACS.memhp.dsl new file mode 100644 index 0000000000..fb6d84c152 --- /dev/null +++ b/tests/data/acpi/q35/FACS.memhp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.mmio64 b/tests/data/acpi/q35/FACS.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.mmio64.dsl b/tests/data/acpi/q35/FACS.mmio64.dsl new file mode 100644 index 0000000000..1a20060749 --- /dev/null +++ b/tests/data/acpi/q35/FACS.mmio64.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.numamem b/tests/data/acpi/q35/FACS.numamem new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.numamem.dsl b/tests/data/acpi/q35/FACS.numamem.dsl new file mode 100644 index 0000000000..740e0bca9a --- /dev/null +++ b/tests/data/acpi/q35/FACS.numamem.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.tis b/tests/data/acpi/q35/FACS.tis new file mode 100644 index 0000000000000000000000000000000000000000..fc67ecc40782bd7fe8921e430d7de67f0bfaad93 GIT binary patch literal 64 PcwTdJbPjf4ARhn#RKNjV literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/FACS.tis.dsl b/tests/data/acpi/q35/FACS.tis.dsl new file mode 100644 index 0000000000..cb35bde06c --- /dev/null +++ b/tests/data/acpi/q35/FACS.tis.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/HMAT.acpihmat.dsl b/tests/data/acpi/q35/HMAT.acpihmat.dsl new file mode 100644 index 0000000000..4abaa94f78 --- /dev/null +++ b/tests/data/acpi/q35/HMAT.acpihmat.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HMAT.dsl b/tests/data/acpi/q35/HMAT.dsl new file mode 100644 index 0000000000..43bc9adc98 --- /dev/null +++ b/tests/data/acpi/q35/HMAT.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.acpihmat b/tests/data/acpi/q35/HPET.acpihmat new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.acpihmat.dsl b/tests/data/acpi/q35/HPET.acpihmat.dsl new file mode 100644 index 0000000000..9806b81069 --- /dev/null +++ b/tests/data/acpi/q35/HPET.acpihmat.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.bridge b/tests/data/acpi/q35/HPET.bridge new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.bridge.dsl b/tests/data/acpi/q35/HPET.bridge.dsl new file mode 100644 index 0000000000..817040df23 --- /dev/null +++ b/tests/data/acpi/q35/HPET.bridge.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.cphp b/tests/data/acpi/q35/HPET.cphp new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.cphp.dsl b/tests/data/acpi/q35/HPET.cphp.dsl new file mode 100644 index 0000000000..4134b96873 --- /dev/null +++ b/tests/data/acpi/q35/HPET.cphp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.dimmpxm b/tests/data/acpi/q35/HPET.dimmpxm new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.dimmpxm.dsl b/tests/data/acpi/q35/HPET.dimmpxm.dsl new file mode 100644 index 0000000000..42a7cc5fd6 --- /dev/null +++ b/tests/data/acpi/q35/HPET.dimmpxm.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.dsl b/tests/data/acpi/q35/HPET.dsl new file mode 100644 index 0000000000..42c40fd653 --- /dev/null +++ b/tests/data/acpi/q35/HPET.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.ipmibt b/tests/data/acpi/q35/HPET.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.ipmibt.dsl b/tests/data/acpi/q35/HPET.ipmibt.dsl new file mode 100644 index 0000000000..9637f4cf81 --- /dev/null +++ b/tests/data/acpi/q35/HPET.ipmibt.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.memhp b/tests/data/acpi/q35/HPET.memhp new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.memhp.dsl b/tests/data/acpi/q35/HPET.memhp.dsl new file mode 100644 index 0000000000..2efab15846 --- /dev/null +++ b/tests/data/acpi/q35/HPET.memhp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.mmio64 b/tests/data/acpi/q35/HPET.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.mmio64.dsl b/tests/data/acpi/q35/HPET.mmio64.dsl new file mode 100644 index 0000000000..dba0368678 --- /dev/null +++ b/tests/data/acpi/q35/HPET.mmio64.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.numamem b/tests/data/acpi/q35/HPET.numamem new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.numamem.dsl b/tests/data/acpi/q35/HPET.numamem.dsl new file mode 100644 index 0000000000..e9d18a59fd --- /dev/null +++ b/tests/data/acpi/q35/HPET.numamem.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.tis b/tests/data/acpi/q35/HPET.tis new file mode 100644 index 0000000000000000000000000000000000000000..df689b8f99c1c43cfd7d63bdede3bcdfd23b7de1 GIT binary patch literal 56 vcwX}ea1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTvjx0SqquV}JqxHY*AN literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/HPET.tis.dsl b/tests/data/acpi/q35/HPET.tis.dsl new file mode 100644 index 0000000000..471cb5b940 --- /dev/null +++ b/tests/data/acpi/q35/HPET.tis.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/MCFG.acpihmat b/tests/data/acpi/q35/MCFG.acpihmat new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.acpihmat.dsl b/tests/data/acpi/q35/MCFG.acpihmat.dsl new file mode 100644 index 0000000000..8d07f64e9d --- /dev/null +++ b/tests/data/acpi/q35/MCFG.acpihmat.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.bridge b/tests/data/acpi/q35/MCFG.bridge new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.bridge.dsl b/tests/data/acpi/q35/MCFG.bridge.dsl new file mode 100644 index 0000000000..6ce54d7228 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.bridge.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.cphp b/tests/data/acpi/q35/MCFG.cphp new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.cphp.dsl b/tests/data/acpi/q35/MCFG.cphp.dsl new file mode 100644 index 0000000000..7ffd7f30db --- /dev/null +++ b/tests/data/acpi/q35/MCFG.cphp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.dimmpxm b/tests/data/acpi/q35/MCFG.dimmpxm new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.dimmpxm.dsl b/tests/data/acpi/q35/MCFG.dimmpxm.dsl new file mode 100644 index 0000000000..dd7373b692 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.dimmpxm.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.dsl b/tests/data/acpi/q35/MCFG.dsl new file mode 100644 index 0000000000..5179d6d707 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.ipmibt b/tests/data/acpi/q35/MCFG.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.ipmibt.dsl b/tests/data/acpi/q35/MCFG.ipmibt.dsl new file mode 100644 index 0000000000..80c372162c --- /dev/null +++ b/tests/data/acpi/q35/MCFG.ipmibt.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.memhp b/tests/data/acpi/q35/MCFG.memhp new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.memhp.dsl b/tests/data/acpi/q35/MCFG.memhp.dsl new file mode 100644 index 0000000000..1b1f666833 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.memhp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.mmio64 b/tests/data/acpi/q35/MCFG.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.mmio64.dsl b/tests/data/acpi/q35/MCFG.mmio64.dsl new file mode 100644 index 0000000000..79be440f72 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.mmio64.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.numamem b/tests/data/acpi/q35/MCFG.numamem new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.numamem.dsl b/tests/data/acpi/q35/MCFG.numamem.dsl new file mode 100644 index 0000000000..30b37074d3 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.numamem.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.tis b/tests/data/acpi/q35/MCFG.tis new file mode 100644 index 0000000000000000000000000000000000000000..79ceb27a038c6e29d098b98dda2e229495f96b7c GIT binary patch literal 60 rcwX~$c5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cDU|3L%*SE304 literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/MCFG.tis.dsl b/tests/data/acpi/q35/MCFG.tis.dsl new file mode 100644 index 0000000000..0a92d698e9 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.tis.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/NFIT.dimmpxm.dsl b/tests/data/acpi/q35/NFIT.dimmpxm.dsl new file mode 100644 index 0000000000..e29b770dca --- /dev/null +++ b/tests/data/acpi/q35/NFIT.dimmpxm.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/NFIT.dsl b/tests/data/acpi/q35/NFIT.dsl new file mode 100644 index 0000000000..8da7718431 --- /dev/null +++ b/tests/data/acpi/q35/NFIT.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SLIT.cphp.dsl b/tests/data/acpi/q35/SLIT.cphp.dsl new file mode 100644 index 0000000000..cb7347fbd4 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SLIT.dsl b/tests/data/acpi/q35/SLIT.dsl new file mode 100644 index 0000000000..89c381bdd0 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SLIT.memhp.dsl b/tests/data/acpi/q35/SLIT.memhp.dsl new file mode 100644 index 0000000000..70b233c0e6 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SRAT.acpihmat.dsl b/tests/data/acpi/q35/SRAT.acpihmat.dsl new file mode 100644 index 0000000000..8a1b47e6b0 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.acpihmat.dsl @@ -0,0 +1,137 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : C0 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 01 [Memory Affinity] +[051h 0081 1] Length : 28 + +[052h 0082 4] Proximity Domain : 00000000 +[056h 0086 2] Reserved1 : 0000 +[058h 0088 8] Base Address : 0000000000000000 +[060h 0096 8] Address Length : 00000000000A0000 +[068h 0104 4] Reserved2 : 00000000 +[06Ch 0108 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[070h 0112 8] Reserved3 : 0000000000000000 + +[078h 0120 1] Subtable Type : 01 [Memory Affinity] +[079h 0121 1] Length : 28 + +[07Ah 0122 4] Proximity Domain : 00000000 +[07Eh 0126 2] Reserved1 : 0000 +[080h 0128 8] Base Address : 0000000000100000 +[088h 0136 8] Address Length : 0000000003F00000 +[090h 0144 4] Reserved2 : 00000000 +[094h 0148 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[098h 0152 8] Reserved3 : 0000000000000000 + +[0A0h 0160 1] Subtable Type : 01 [Memory Affinity] +[0A1h 0161 1] Length : 28 + +[0A2h 0162 4] Proximity Domain : 00000001 +[0A6h 0166 2] Reserved1 : 0000 +[0A8h 0168 8] Base Address : 0000000004000000 +[0B0h 0176 8] Address Length : 0000000004000000 +[0B8h 0184 4] Reserved2 : 00000000 +[0BCh 0188 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0C0h 0192 8] Reserved3 : 0000000000000000 + +[0C8h 0200 1] Subtable Type : 01 [Memory Affinity] +[0C9h 0201 1] Length : 28 + +[0CAh 0202 4] Proximity Domain : 00000000 +[0CEh 0206 2] Reserved1 : 0000 +[0D0h 0208 8] Base Address : 0000000000000000 +[0D8h 0216 8] Address Length : 0000000000000000 +[0E0h 0224 4] Reserved2 : 00000000 +[0E4h 0228 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E8h 0232 8] Reserved3 : 0000000000000000 + +[0F0h 0240 1] Subtable Type : 01 [Memory Affinity] +[0F1h 0241 1] Length : 28 + +[0F2h 0242 4] Proximity Domain : 00000001 +[0F6h 0246 2] Reserved1 : 0000 +[0F8h 0248 8] Base Address : 0000000100000000 +[100h 0256 8] Address Length : 00000000B8000000 +[108h 0264 4] Reserved2 : 00000000 +[10Ch 0268 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[110h 0272 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 280 (0x118) + + 0000: 53 52 41 54 18 01 00 00 01 C0 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0060: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0080: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0090: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00B0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0100: 00 00 00 B8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0110: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.cphp.dsl b/tests/data/acpi/q35/SRAT.cphp.dsl new file mode 100644 index 0000000000..f0023db38d --- /dev/null +++ b/tests/data/acpi/q35/SRAT.cphp.dsl @@ -0,0 +1,168 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000130 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 36 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 00 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 01 +[063h 0099 1] Apic ID : 04 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[071h 0113 1] Length : 10 + +[072h 0114 1] Proximity Domain Low(8) : 01 +[073h 0115 1] Apic ID : 05 +[074h 0116 4] Flags (decoded below) : 00000001 + Enabled : 1 +[078h 0120 1] Local Sapic EID : 00 +[079h 0121 3] Proximity Domain High(24) : 000000 +[07Ch 0124 4] Clock Domain : 00000000 + +[080h 0128 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[081h 0129 1] Length : 10 + +[082h 0130 1] Proximity Domain Low(8) : 01 +[083h 0131 1] Apic ID : 06 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 +[088h 0136 1] Local Sapic EID : 00 +[089h 0137 3] Proximity Domain High(24) : 000000 +[08Ch 0140 4] Clock Domain : 00000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 00000000000A0000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000100000 +[0C8h 0200 8] Address Length : 0000000003F00000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000004000000 +[0F0h 0240 8] Address Length : 0000000004000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +[108h 0264 1] Subtable Type : 01 [Memory Affinity] +[109h 0265 1] Length : 28 + +[10Ah 0266 4] Proximity Domain : 00000000 +[10Eh 0270 2] Reserved1 : 0000 +[110h 0272 8] Base Address : 0000000000000000 +[118h 0280 8] Address Length : 0000000000000000 +[120h 0288 4] Reserved2 : 00000000 +[124h 0292 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[128h 0296 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 304 (0x130) + + 0000: 53 52 41 54 30 01 00 00 01 36 42 4F 43 48 53 20 // SRAT0....6BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 00 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 01 04 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 10 01 05 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 10 01 06 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 00D0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00F0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.dimmpxm.dsl b/tests/data/acpi/q35/SRAT.dimmpxm.dsl new file mode 100644 index 0000000000..2cfe6994f5 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.dimmpxm.dsl @@ -0,0 +1,194 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000188 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 68 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 01 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 02 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 03 +[063h 0099 1] Apic ID : 03 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 01 [Memory Affinity] +[071h 0113 1] Length : 28 + +[072h 0114 4] Proximity Domain : 00000000 +[076h 0118 2] Reserved1 : 0000 +[078h 0120 8] Base Address : 0000000000000000 +[080h 0128 8] Address Length : 00000000000A0000 +[088h 0136 4] Reserved2 : 00000000 +[08Ch 0140 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[090h 0144 8] Reserved3 : 0000000000000000 + +[098h 0152 1] Subtable Type : 01 [Memory Affinity] +[099h 0153 1] Length : 28 + +[09Ah 0154 4] Proximity Domain : 00000000 +[09Eh 0158 2] Reserved1 : 0000 +[0A0h 0160 8] Base Address : 0000000000100000 +[0A8h 0168 8] Address Length : 0000000001F00000 +[0B0h 0176 4] Reserved2 : 00000000 +[0B4h 0180 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B8h 0184 8] Reserved3 : 0000000000000000 + +[0C0h 0192 1] Subtable Type : 01 [Memory Affinity] +[0C1h 0193 1] Length : 28 + +[0C2h 0194 4] Proximity Domain : 00000001 +[0C6h 0198 2] Reserved1 : 0000 +[0C8h 0200 8] Base Address : 0000000002000000 +[0D0h 0208 8] Address Length : 0000000002000000 +[0D8h 0216 4] Reserved2 : 00000000 +[0DCh 0220 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E0h 0224 8] Reserved3 : 0000000000000000 + +[0E8h 0232 1] Subtable Type : 01 [Memory Affinity] +[0E9h 0233 1] Length : 28 + +[0EAh 0234 4] Proximity Domain : 00000002 +[0EEh 0238 2] Reserved1 : 0000 +[0F0h 0240 8] Base Address : 0000000004000000 +[0F8h 0248 8] Address Length : 0000000002000000 +[100h 0256 4] Reserved2 : 00000000 +[104h 0260 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[108h 0264 8] Reserved3 : 0000000000000000 + +[110h 0272 1] Subtable Type : 01 [Memory Affinity] +[111h 0273 1] Length : 28 + +[112h 0274 4] Proximity Domain : 00000003 +[116h 0278 2] Reserved1 : 0000 +[118h 0280 8] Base Address : 0000000006000000 +[120h 0288 8] Address Length : 0000000002000000 +[128h 0296 4] Reserved2 : 00000000 +[12Ch 0300 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[130h 0304 8] Reserved3 : 0000000000000000 + +[138h 0312 1] Subtable Type : 01 [Memory Affinity] +[139h 0313 1] Length : 28 + +[13Ah 0314 4] Proximity Domain : 00000002 +[13Eh 0318 2] Reserved1 : 0000 +[140h 0320 8] Base Address : 0000000108000000 +[148h 0328 8] Address Length : 0000000008000000 +[150h 0336 4] Reserved2 : 00000000 +[154h 0340 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[158h 0344 8] Reserved3 : 0000000000000000 + +[160h 0352 1] Subtable Type : 01 [Memory Affinity] +[161h 0353 1] Length : 28 + +[162h 0354 4] Proximity Domain : 00000003 +[166h 0358 2] Reserved1 : 0000 +[168h 0360 8] Base Address : 0000000100000000 +[170h 0368 8] Address Length : 00000000F8000000 +[178h 0376 4] Reserved2 : 00000000 +[17Ch 0380 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[180h 0384 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 392 (0x188) + + 0000: 53 52 41 54 88 01 00 00 01 68 42 4F 43 48 53 20 // SRAT.....hBOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 01 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 02 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 03 03 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0080: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00A0: 00 00 10 00 00 00 00 00 00 00 F0 01 00 00 00 00 // ................ + 00B0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 01 28 01 00 00 00 00 00 00 00 00 02 00 00 00 00 // .(.............. + 00D0: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 00F0: 00 00 00 04 00 00 00 00 00 00 00 02 00 00 00 00 // ................ + 0100: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0110: 01 28 03 00 00 00 00 00 00 00 00 06 00 00 00 00 // .(.............. + 0120: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0130: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 0140: 00 00 00 08 01 00 00 00 00 00 00 08 00 00 00 00 // ................ + 0150: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0160: 01 28 03 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0170: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0180: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.dsl b/tests/data/acpi/q35/SRAT.dsl new file mode 100644 index 0000000000..5f4278994e --- /dev/null +++ b/tests/data/acpi/q35/SRAT.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.memhp.dsl b/tests/data/acpi/q35/SRAT.memhp.dsl new file mode 100644 index 0000000000..a5f27214eb --- /dev/null +++ b/tests/data/acpi/q35/SRAT.memhp.dsl @@ -0,0 +1,125 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000108 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A2 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000000 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000000 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000003F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000001 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000004000000 +[0A0h 0160 8] Address Length : 0000000004000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000100000000 +[0F0h 0240 8] Address Length : 00000000F8000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 264 (0x108) + + 0000: 53 52 41 54 08 01 00 00 01 A2 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00A0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 00F0: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.mmio64.dsl b/tests/data/acpi/q35/SRAT.mmio64.dsl new file mode 100644 index 0000000000..0065c21de4 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.mmio64.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 3B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000000 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000000 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000100000000 +[0C8h 0200 8] Address Length : 00000000B8000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 3B 42 4F 43 48 53 20 // SRAT.....;BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 01 00 00 00 00 00 00 B8 00 00 00 00 // ................ + 00D0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.numamem.dsl b/tests/data/acpi/q35/SRAT.numamem.dsl new file mode 100644 index 0000000000..e8de953ae2 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.numamem.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SSDT.dsl b/tests/data/acpi/q35/SSDT.dsl new file mode 100644 index 0000000000..49df22f93d --- /dev/null +++ b/tests/data/acpi/q35/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002DE (734) + * Revision 0x01 + * Checksum 0x46 + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x07FFF000) +} + diff --git a/tests/data/acpi/q35/TPM2.dsl b/tests/data/acpi/q35/TPM2.dsl new file mode 100644 index 0000000000..8568152ccf --- /dev/null +++ b/tests/data/acpi/q35/TPM2.dsl @@ -0,0 +1,38 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/TPM2.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[004h 0004 4] Table Length : 0000004C +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : 72 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCTPM2" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 2] Platform Class : 0000 +[026h 0038 2] Reserved : 0000 +[028h 0040 8] Control Address : 0000000000000000 +[030h 0048 4] Start Method : 06 [Memory Mapped I/O] + +[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00 +[040h 0064 4] Minimum Log Length : 00010000 +[044h 0068 8] Log Address : 0000000007FF0000 + +Raw Table Data: Length 76 (0x4C) + + 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS + 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/TPM2.tis.dsl b/tests/data/acpi/q35/TPM2.tis.dsl new file mode 100644 index 0000000000..420643ab2b --- /dev/null +++ b/tests/data/acpi/q35/TPM2.tis.dsl @@ -0,0 +1,38 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/TPM2.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[004h 0004 4] Table Length : 0000004C +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : 72 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCTPM2" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 2] Platform Class : 0000 +[026h 0038 2] Reserved : 0000 +[028h 0040 8] Control Address : 0000000000000000 +[030h 0048 4] Start Method : 06 [Memory Mapped I/O] + +[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00 +[040h 0064 4] Minimum Log Length : 00010000 +[044h 0068 8] Log Address : 0000000007FF0000 + +Raw Table Data: Length 76 (0x4C) + + 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS + 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/WAET.acpihmat b/tests/data/acpi/q35/WAET.acpihmat new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.acpihmat.dsl b/tests/data/acpi/q35/WAET.acpihmat.dsl new file mode 100644 index 0000000000..12a4fced5c --- /dev/null +++ b/tests/data/acpi/q35/WAET.acpihmat.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.bridge b/tests/data/acpi/q35/WAET.bridge new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.bridge.dsl b/tests/data/acpi/q35/WAET.bridge.dsl new file mode 100644 index 0000000000..48effe4c6e --- /dev/null +++ b/tests/data/acpi/q35/WAET.bridge.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.cphp b/tests/data/acpi/q35/WAET.cphp new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.cphp.dsl b/tests/data/acpi/q35/WAET.cphp.dsl new file mode 100644 index 0000000000..aadebd53e8 --- /dev/null +++ b/tests/data/acpi/q35/WAET.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.dimmpxm b/tests/data/acpi/q35/WAET.dimmpxm new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.dimmpxm.dsl b/tests/data/acpi/q35/WAET.dimmpxm.dsl new file mode 100644 index 0000000000..7ad316b118 --- /dev/null +++ b/tests/data/acpi/q35/WAET.dimmpxm.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.dsl b/tests/data/acpi/q35/WAET.dsl new file mode 100644 index 0000000000..b48db4efca --- /dev/null +++ b/tests/data/acpi/q35/WAET.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.ipmibt b/tests/data/acpi/q35/WAET.ipmibt new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.ipmibt.dsl b/tests/data/acpi/q35/WAET.ipmibt.dsl new file mode 100644 index 0000000000..40cb1d5649 --- /dev/null +++ b/tests/data/acpi/q35/WAET.ipmibt.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.memhp b/tests/data/acpi/q35/WAET.memhp new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.memhp.dsl b/tests/data/acpi/q35/WAET.memhp.dsl new file mode 100644 index 0000000000..e27f54d4dd --- /dev/null +++ b/tests/data/acpi/q35/WAET.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.mmio64 b/tests/data/acpi/q35/WAET.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.mmio64.dsl b/tests/data/acpi/q35/WAET.mmio64.dsl new file mode 100644 index 0000000000..98f3aaf569 --- /dev/null +++ b/tests/data/acpi/q35/WAET.mmio64.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.numamem b/tests/data/acpi/q35/WAET.numamem new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.numamem.dsl b/tests/data/acpi/q35/WAET.numamem.dsl new file mode 100644 index 0000000000..738c75ca6c --- /dev/null +++ b/tests/data/acpi/q35/WAET.numamem.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.tis b/tests/data/acpi/q35/WAET.tis new file mode 100644 index 0000000000000000000000000000000000000000..c2240f58dff6b2f765386b5a2e506fda4800be3e GIT binary patch literal 40 mcwP&4bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS literal 0 HcwPel00001 diff --git a/tests/data/acpi/q35/WAET.tis.dsl b/tests/data/acpi/q35/WAET.tis.dsl new file mode 100644 index 0000000000..869ebe2b4a --- /dev/null +++ b/tests/data/acpi/q35/WAET.tis.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/virt/APIC.dsl b/tests/data/acpi/virt/APIC.dsl new file mode 100644 index 0000000000..d334cef533 --- /dev/null +++ b/tests/data/acpi/virt/APIC.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.memhp.dsl b/tests/data/acpi/virt/APIC.memhp.dsl new file mode 100644 index 0000000000..9b86f7b984 --- /dev/null +++ b/tests/data/acpi/virt/APIC.memhp.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.numamem.dsl b/tests/data/acpi/virt/APIC.numamem.dsl new file mode 100644 index 0000000000..2d43338766 --- /dev/null +++ b/tests/data/acpi/virt/APIC.numamem.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/DSDT.dsl b/tests/data/acpi/virt/DSDT.dsl new file mode 100644 index 0000000000..58368ff44c --- /dev/null +++ b/tests/data/acpi/virt/DSDT.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001450 (5200) + * Revision 0x02 + * Checksum 0xFA + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, Zero) // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.memhp.dsl b/tests/data/acpi/virt/DSDT.memhp.dsl new file mode 100644 index 0000000000..84f3c51867 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.memhp.dsl @@ -0,0 +1,2215 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000019A6 (6566) + * Revision 0x02 + * Checksum 0x02 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & One) == One)) + { + \_SB.MHPC.MSCN () + } + + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + + If (((Local0 & 0x04) == 0x04)) + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + } + + Device (\_SB.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09070000, // Address Base + 0x00000018, // Address Length + ) + }) + OperationRegion (HPMR, SystemMemory, 0x09070000, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y00, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.numamem.dsl b/tests/data/acpi/virt/DSDT.numamem.dsl new file mode 100644 index 0000000000..6603d31a01 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.numamem.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001455 (5205) + * Revision 0x02 + * Checksum 0xE1 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/FACP.dsl b/tests/data/acpi/virt/FACP.dsl new file mode 100644 index 0000000000..2c73796f89 --- /dev/null +++ b/tests/data/acpi/virt/FACP.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.memhp.dsl b/tests/data/acpi/virt/FACP.memhp.dsl new file mode 100644 index 0000000000..0083b95ef7 --- /dev/null +++ b/tests/data/acpi/virt/FACP.memhp.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.numamem.dsl b/tests/data/acpi/virt/FACP.numamem.dsl new file mode 100644 index 0000000000..aee15bd4c2 --- /dev/null +++ b/tests/data/acpi/virt/FACP.numamem.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/GTDT.dsl b/tests/data/acpi/virt/GTDT.dsl new file mode 100644 index 0000000000..1ab06dd3c2 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.memhp.dsl b/tests/data/acpi/virt/GTDT.memhp.dsl new file mode 100644 index 0000000000..d78bb092c5 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.memhp.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.numamem.dsl b/tests/data/acpi/virt/GTDT.numamem.dsl new file mode 100644 index 0000000000..5c3c2a83db --- /dev/null +++ b/tests/data/acpi/virt/GTDT.numamem.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/MCFG.dsl b/tests/data/acpi/virt/MCFG.dsl new file mode 100644 index 0000000000..f09c86f487 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.memhp.dsl b/tests/data/acpi/virt/MCFG.memhp.dsl new file mode 100644 index 0000000000..b03a6384e8 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.memhp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.numamem.dsl b/tests/data/acpi/virt/MCFG.numamem.dsl new file mode 100644 index 0000000000..303df803f5 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.numamem.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/NFIT.dsl b/tests/data/acpi/virt/NFIT.dsl new file mode 100644 index 0000000000..947ba0f6a4 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/NFIT.memhp.dsl b/tests/data/acpi/virt/NFIT.memhp.dsl new file mode 100644 index 0000000000..84511bff96 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.memhp.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SLIT.dsl b/tests/data/acpi/virt/SLIT.dsl new file mode 100644 index 0000000000..34276fca96 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SLIT.memhp.dsl b/tests/data/acpi/virt/SLIT.memhp.dsl new file mode 100644 index 0000000000..a17f948af2 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SPCR.dsl b/tests/data/acpi/virt/SPCR.dsl new file mode 100644 index 0000000000..3c271412cf --- /dev/null +++ b/tests/data/acpi/virt/SPCR.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.memhp.dsl b/tests/data/acpi/virt/SPCR.memhp.dsl new file mode 100644 index 0000000000..81e00457cc --- /dev/null +++ b/tests/data/acpi/virt/SPCR.memhp.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.numamem.dsl b/tests/data/acpi/virt/SPCR.numamem.dsl new file mode 100644 index 0000000000..faf6729797 --- /dev/null +++ b/tests/data/acpi/virt/SPCR.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SRAT.dsl b/tests/data/acpi/virt/SRAT.dsl new file mode 100644 index 0000000000..f267aabc67 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SRAT.memhp.dsl b/tests/data/acpi/virt/SRAT.memhp.dsl new file mode 100644 index 0000000000..3f311e6be0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.memhp.dsl @@ -0,0 +1,107 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E2 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 5C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +[06Ah 0106 1] Subtable Type : 01 [Memory Affinity] +[06Bh 0107 1] Length : 28 + +[06Ch 0108 4] Proximity Domain : 00000001 +[070h 0112 2] Reserved1 : 0000 +[072h 0114 8] Base Address : 0000000048000000 +[07Ah 0122 8] Address Length : 0000000008000000 +[082h 0130 4] Reserved2 : 00000000 +[086h 0134 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[08Ah 0138 8] Reserved3 : 0000000000000000 + +[092h 0146 1] Subtable Type : 01 [Memory Affinity] +[093h 0147 1] Length : 28 + +[094h 0148 4] Proximity Domain : 00000001 +[098h 0152 2] Reserved1 : 0000 +[09Ah 0154 8] Base Address : 0000000088000000 +[0A2h 0162 8] Address Length : 0000000008000000 +[0AAh 0170 4] Reserved2 : 00000000 +[0AEh 0174 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[0B2h 0178 8] Reserved3 : 0000000000000000 + +[0BAh 0186 1] Subtable Type : 01 [Memory Affinity] +[0BBh 0187 1] Length : 28 + +[0BCh 0188 4] Proximity Domain : 00000001 +[0C0h 0192 2] Reserved1 : 0000 +[0C2h 0194 8] Base Address : 0000000080000000 +[0CAh 0202 8] Address Length : 00000000F0000000 +[0D2h 0210 4] Reserved2 : 00000000 +[0D6h 0214 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[0DAh 0218 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 226 (0xE2) + + 0000: 53 52 41 54 E2 00 00 00 03 5C 42 4F 43 48 53 20 // SRAT.....\BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 0070: 00 00 00 00 00 48 00 00 00 00 00 00 00 08 00 00 // .....H.......... + 0080: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 01 28 01 00 00 00 00 00 00 00 00 88 00 00 // ...(............ + 00A0: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 05 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 00C0: 00 00 00 00 00 80 00 00 00 00 00 00 00 F0 00 00 // ................ + 00D0: 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 // .. diff --git a/tests/data/acpi/virt/SRAT.numamem.dsl b/tests/data/acpi/virt/SRAT.numamem.dsl new file mode 100644 index 0000000000..b6e59b1af0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SSDT.dsl b/tests/data/acpi/virt/SSDT.dsl new file mode 100644 index 0000000000..cb220787b4 --- /dev/null +++ b/tests/data/acpi/virt/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/SSDT.memhp, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002E0 (736) + * Revision 0x01 + * Checksum 0x3F + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemMemory, 0x09090000, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x43D10000) +} + diff --git a/tests/data/uefi-boot-images/bios-tables-test.x86_64.iso.raw b/tests/data/uefi-boot-images/bios-tables-test.x86_64.iso.raw new file mode 100644 index 0000000000000000000000000000000000000000..bd43ba50a3b25bdf4108cf920a26acc93cc45555 GIT binary patch literal 425984 zcwX(@4SZDPo#^p1fj~fU(kcknmxG2jQAj3$NK|YlFL1_ANIoP1Eh>)51hRxoI++o0 zbvHDVE@MpV-NoCwb$9K(?T6g1_tv|$YFV!hMg@GiqPEtSt)ha?I9P#g1FqG%|K~Yp z@(yTqcl+`Fz8{nG_MGSWKhJs2bDlFJU>E=Z000000000000000000000000000000 z00000000000000000000000000KipV;qer^48L!A{Wa!^l~=5&t~$x_On!SuEKbZN z|EV7%C&!p-@0xnn(BT>C*M-JRduyhVqZT>FQkObuVpit-lLUnS0Lv#xl0 zylmclk7tp2bzx1VcSUXW@}jE?Ys)R4UwY*-okks2X)aS8@hiSMv#!#6vhMirW4@=j z#ItbzrNzaUF7#aL@#Kuz;Tgpklfq@3suX;-8Nir@E<0KlJ)wDbNC0000006x21`a5>s{{a91008(b({KJW`2YX_0001h z&$6+9#(v|(S*I<^&KdkO_NPqY@)+mXDbBI?7?~7?y?sWRuex?kowuxTskiQmVqYFTx4U17OS3jhEiH|wTl_qEi}zR7%6okAeA6_~xZu&%x88SQU*xov z51jGOlZ|I{Z%7@Uf8f~}&(2DHShudZ-IV`YLlHAz-V_Q&0ynh;&Bo^T^@XNc(-I7{ z2hHZz_F#C#@urqgTia$c(Aqd{YFjwi-Y%<~&Go^}W+Y@r!g6G7pt;p7EG#sqO+8Vy z@R8L2@OWCuzR{T6VNAK#IPGxyROjHcgzNwRw_$^Nj$u4@!`;j8UT!b#c@ zNlFC(0RNdz{QS3{-zR?l+w%kU{J&<=LR0-cK_ib(G)gZ&Nx=XB;6F{(S5KAV#5zuu z;3KH1G>pb?jQp(Nuu*87Cew=>FExx(=dT&eJ8x)RF`b{$)SM%e?xX(gu(_v7FwFiE ziA$C_vOM=xi9d$INN`ic7^?H|x@VZOyRb132^jXVdoLSW4p(XzeTCs*OQ^w)H50R1 zj!IW%d_vvXzg}n<{k7JXLn;)1_q4AsG7PKdy1Y_l6Un*K5uoGma3I0R{Ymid}q2Q=l1MdB=6qb$mGPiGYlg&rPqvP zC+=70ZFyXkwz~iJ>{XJabHA&9r4|3bwO0H^31qPfBp%DVQ7`YvTPMrJ3+Z$^))zU? z>e?5bDN((5feLfl6bWv}6;hEzi6ltOlV4qjBc)bPM8$rG&chdfd58LkiLCe$zf>VV zG5bs%dhexULqBSVE&-}2R^K2I{$zn+>`kZ`yQcj>*4=mY^;_}dR{S|@=es$+_6PZ}C)pGe=eO7u`>h*qaofSV^Z^eHh6@1_7Jmh(Dvf=M( z%$pm3TZ*fS?@!c9MBR0HbEQT*=15fOeu?Myvp%==%;-L=^Kp+Ae|h!w-s}2TNvZz$ zp334q(q1q5>wNLw)%)YmI?ZdT zrsx{5;*aF*HSCsF|4Kw;;lPt-bYY_TL*3A`tWNv5M4J7KH1>`%X^`kysRe@vqLWke z<($YFiA(KsE~)BDMc*|S^7dfbG}@oyFN&#i~Ew_`kV}0UFqmA zQb#Mg=lSLvMrGGK(P_J4dEb|8)m@XiIq}*D_64shIdrqS;4hjwpP1ycqgM3@OA@Gq zyHoc`E|W*)qW(qflqd1sQMr7ksL) zlkN#8-QOou(s)wjQm4ps28%R?iqy5aI`Qlu#+0{jSb2YGmlsgwHLLRG43+m|C*Ajw zfBvDWrx}@C)pa29<cbxG-I!a_gx80<^^fNy9j~=&Nhpo7s zA~kbFT3O$lS(i?t1NXWgJUcSg>wa{ZYv=x)R911{l)e7$dj<=7ICH{xtc&b=tITs$ zAMJ_do#V2%cdPx~&VIR5FR1F;=e{eJmyrGbEAG)Dgy(iVqIVdP3p?I2r3@9cJNE4} z>~mE~#V=UL{x#`#8^)G5N@uGuk56;QHs|QIIT5$~p6c$pXo_6m7jx_YJDdQ$J6ul4 zy_t}^?Th1c?XuFl$E)bDN_8He=Z?)$|F+s?vVO5Uwp6W8m&&+f`B^%F>5k2iov9jG zzr-DLx%A$-?${Ky_i|Y;*=Wk|Vs~fMK33?CJ!NO^amQ*^s