| commit | d17bcae5f7e9f949052a1f126a7f23e7279b6d96 | |
| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | |
| Mon, 16 Oct 2023 11:17:32 +0000 (16 12:17 +0100) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 7 Nov 2023 01:02:17 +0000 (7 11:02 +1000) | ||
| tree | 4f7a0b3296e3b4a29055a16d9563ba243349383f | treesnapshot (tar.gz zip) |
| parent | a7b69170254b15b5a40b318ed5559084ccfc466b | commitdiff |
target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu_helper.c | diffblobblamehistory |