| commit | baf21eebc3e1026d21d94fdf8ca470050e49968f | |
| author | Marcin Nowakowski <marcin.nowakowski@fungible.com> | |
| Fri, 30 Jun 2023 07:28:06 +0000 (30 09:28 +0200) | ||
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | |
| Mon, 10 Jul 2023 21:33:38 +0000 (10 23:33 +0200) | ||
| tree | 8fc98f48948de62a2cbc46e55f485466b0759677 | treesnapshot (tar.gz zip) |
| parent | 8aedfb64cdcfa60a077c66e802f6c65a419631de | commitdiff |
target/mips: enable GINVx support for I6400 and I6500
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].
Cc: qemu-stable@nongnu.org
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].
Cc: qemu-stable@nongnu.org
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| target/mips/cpu-defs.c.inc | diffblobblamehistory |