| commit | a71e26461464fc50ef84279dc7fceb40960182c1 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 6 Feb 2024 13:29:28 +0000 (6 13:29 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 15 Feb 2024 14:32:39 +0000 (15 14:32 +0000) | ||
| tree | ef0217ce020d6716d92d5f10305c6a889c4bf71e | treesnapshot (tar.gz zip) |
| parent | 9220b09d3b1294967be67b1baeeb928187245594 | commitdiff |
hw/arm/mps3r: Add UARTs
This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.
Connect and wire them all up; this involves some OR gates where
multiple overflow interrupts are wired into one GIC input.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.
Connect and wire them all up; this involves some OR gates where
multiple overflow interrupts are wired into one GIC input.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
| hw/arm/mps3r.c | diffblobblamehistory |