| commit | 888050cf519eb5995424cf415f4f8f269de96824 | |
| author | Nicholas Piggin <npiggin@gmail.com> | |
| Tue, 20 Jun 2023 13:10:41 +0000 (20 23:10 +1000) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Sun, 25 Jun 2023 20:41:30 +0000 (25 22:41 +0200) | ||
| tree | d6ff1489fd56e8fc9c586661014eeec74a634f96 | treesnapshot (tar.gz zip) |
| parent | 6b8a05373bf142fe5fd3839c3675da005bfc9b49 | commitdiff |
target/ppc: Fix instruction loading endianness in alignment interrupt
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| target/ppc/excp_helper.c | diffblobblamehistory |