| commit | 5b49a34c6800d0cb917f959d8e75e5775f0fac3f | |
| author | Damien Hedde <damien.hedde@greensocs.com> | |
| Mon, 6 Apr 2020 13:52:50 +0000 (6 15:52 +0200) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 30 Apr 2020 14:35:41 +0000 (30 15:35 +0100) | ||
| tree | 962ed8af2d77f48e347ce85e7859c6320490656e | treesnapshot (tar.gz zip) |
| parent | b636db306e06ee1c267d6e15e3b5bc109252617f | commitdiff |
hw/arm/xilinx_zynq: connect uart clocks to slcr
Add the connection between the slcr's output clocks and the uarts inputs.
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
(the default frequency). This clock is used to feed the slcr's input
clock.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add the connection between the slcr's output clocks and the uarts inputs.
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
(the default frequency). This clock is used to feed the slcr's input
clock.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/xilinx_zynq.c | diffblobblamehistory |