| commit | 42bea956f6f7477c06186c7add62fa0107a27a9c | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 7 Jun 2023 04:39:43 +0000 (7 06:39 +0200) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Thu, 15 Jun 2023 16:35:58 +0000 (15 18:35 +0200) | ||
| tree | cd064670357d84634a6f10abcbf1564df3bc76bf | treesnapshot (tar.gz zip) |
| parent | f65f6ad5a749bc2d24a083da3544f47a19e7e81f | commitdiff |
target/arm: Allow users to set the number of VFP registers
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
have 16 64-bit FPU registers and not 32 registers. Let users set the
number of VFP registers with a CPU property.
The primary use case of this property is for the Cortex A7 of the
Aspeed AST2600 SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
have 16 64-bit FPU registers and not 32 registers. Let users set the
number of VFP registers with a CPU property.
The primary use case of this property is for the Cortex A7 of the
Aspeed AST2600 SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/arm/aspeed_ast2600.c | diffblobblamehistory | |
| target/arm/cpu.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory |