| commit | 2808d3b38a5232e263338e1b812bb1f6c2d56bcf | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 7 Mar 2024 12:19:03 +0000 (7 12:19 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 7 Mar 2024 12:19:03 +0000 (7 12:19 +0000) | ||
| tree | bdbed0d02bd0305e5c1645eacc0f6fcd7d002ac0 | treesnapshot (tar.gz zip) |
| parent | 485eb324e352a53bdf99f90511bd546eebab68f5 | commitdiff |
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
implemented. This is similar to the existing CNTVOFF_EL2, except
that it controls a hypervisor-adjustable offset made to the physical
counter and timer.
Implement the handling for this register, which includes control/trap
bits in SCR_EL3 and CNTHCTL_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
implemented. This is similar to the existing CNTVOFF_EL2, except
that it controls a hypervisor-adjustable offset made to the physical
counter and timer.
Implement the handling for this register, which includes control/trap
bits in SCR_EL3 and CNTHCTL_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
| target/arm/cpu-features.h | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/helper.c | diffblobblamehistory | |
| target/arm/trace-events | diffblobblamehistory |