cpu.c

   1 /*
   2  * Target-specific parts of the CPU object
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22
  23 #include "exec/target_page.h"
  24 #include "hw/qdev-core.h"
  25 #include "hw/qdev-properties.h"
  26 #include "qemu/error-report.h"
  27 #include "migration/vmstate.h"
  28 #ifdef CONFIG_USER_ONLY
  29 #include "qemu.h"
  30 #else
  31 #include "hw/core/sysemu-cpu-ops.h"
  32 #include "exec/address-spaces.h"
  33 #endif
  34 #include "sysemu/cpus.h"
  35 #include "sysemu/tcg.h"
  36 #include "exec/replay-core.h"
  37 #include "exec/cpu-common.h"
  38 #include "exec/exec-all.h"
  39 #include "exec/tb-flush.h"
  40 #include "exec/translate-all.h"
  41 #include "exec/log.h"
  42 #include "hw/core/accel-cpu.h"
  43 #include "trace/trace-root.h"
  44 #include "qemu/accel.h"
  45 #include "qemu/plugin.h"
  46
  47 uintptr_t qemu_host_page_size;
  48 intptr_t qemu_host_page_mask;
  49
  50 #ifndef CONFIG_USER_ONLY
  51 static int cpu_common_post_load(void *opaque, int version_id)
  52 {
  53     CPUState *cpu = opaque;
  54
  55     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
  56        version_id is increased. */
  57     cpu->interrupt_request &= ~0x01;
  58     tlb_flush(cpu);
  59
  60     /* loadvm has just updated the content of RAM, bypassing the
  61      * usual mechanisms that ensure we flush TBs for writes to
  62      * memory we've translated code from. So we must flush all TBs,
  63      * which will now be stale.
  64      */
  65     tb_flush(cpu);
  66
  67     return 0;
  68 }
  69
  70 static int cpu_common_pre_load(void *opaque)
  71 {
  72     CPUState *cpu = opaque;
  73
  74     cpu->exception_index = -1;
  75
  76     return 0;
  77 }
  78
  79 static bool cpu_common_exception_index_needed(void *opaque)
  80 {
  81     CPUState *cpu = opaque;
  82
  83     return tcg_enabled() && cpu->exception_index != -1;
  84 }
  85
  86 static const VMStateDescription vmstate_cpu_common_exception_index = {
  87     .name = "cpu_common/exception_index",
  88     .version_id = 1,
  89     .minimum_version_id = 1,
  90     .needed = cpu_common_exception_index_needed,
  91     .fields = (VMStateField[]) {
  92         VMSTATE_INT32(exception_index, CPUState),
  93         VMSTATE_END_OF_LIST()
  94     }
  95 };
  96
  97 static bool cpu_common_crash_occurred_needed(void *opaque)
  98 {
  99     CPUState *cpu = opaque;
 100
 101     return cpu->crash_occurred;
 102 }
 103
 104 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
 105     .name = "cpu_common/crash_occurred",
 106     .version_id = 1,
 107     .minimum_version_id = 1,
 108     .needed = cpu_common_crash_occurred_needed,
 109     .fields = (VMStateField[]) {
 110         VMSTATE_BOOL(crash_occurred, CPUState),
 111         VMSTATE_END_OF_LIST()
 112     }
 113 };
 114
 115 const VMStateDescription vmstate_cpu_common = {
 116     .name = "cpu_common",
 117     .version_id = 1,
 118     .minimum_version_id = 1,
 119     .pre_load = cpu_common_pre_load,
 120     .post_load = cpu_common_post_load,
 121     .fields = (VMStateField[]) {
 122         VMSTATE_UINT32(halted, CPUState),
 123         VMSTATE_UINT32(interrupt_request, CPUState),
 124         VMSTATE_END_OF_LIST()
 125     },
 126     .subsections = (const VMStateDescription*[]) {
 127         &vmstate_cpu_common_exception_index,
 128         &vmstate_cpu_common_crash_occurred,
 129         NULL
 130     }
 131 };
 132 #endif
 133
 134 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 135 {
 136     /* cache the cpu class for the hotpath */
 137     cpu->cc = CPU_GET_CLASS(cpu);
 138
 139     if (!accel_cpu_common_realize(cpu, errp)) {
 140         return;
 141     }
 142
 143     /* NB: errp parameter is unused currently */
 144     if (tcg_enabled()) {
 145         tcg_exec_realizefn(cpu, errp);
 146     }
 147
 148     /* Wait until cpu initialization complete before exposing cpu. */
 149     cpu_list_add(cpu);
 150
 151     /* Plugin initialization must wait until cpu_index assigned. */
 152     if (tcg_enabled()) {
 153         qemu_plugin_vcpu_init_hook(cpu);
 154     }
 155
 156 #ifdef CONFIG_USER_ONLY
 157     assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
 158            qdev_get_vmsd(DEVICE(cpu))->unmigratable);
 159 #else
 160     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 161         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
 162     }
 163     if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
 164         vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
 165     }
 166 #endif /* CONFIG_USER_ONLY */
 167 }
 168
 169 void cpu_exec_unrealizefn(CPUState *cpu)
 170 {
 171 #ifndef CONFIG_USER_ONLY
 172     CPUClass *cc = CPU_GET_CLASS(cpu);
 173
 174     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 175         vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
 176     }
 177     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 178         vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
 179     }
 180 #endif
 181
 182     /* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
 183     if (tcg_enabled()) {
 184         qemu_plugin_vcpu_exit_hook(cpu);
 185     }
 186
 187     cpu_list_remove(cpu);
 188     /*
 189      * Now that the vCPU has been removed from the RCU list, we can call
 190      * tcg_exec_unrealizefn and
 191      * accel_cpu_common_unrealize, which may free fields using call_rcu.
 192      */
 193     accel_cpu_common_unrealize(cpu);
 194     if (tcg_enabled()) {
 195         tcg_exec_unrealizefn(cpu);
 196     }
 197 }
 198
 199 /*
 200  * This can't go in hw/core/cpu.c because that file is compiled only
 201  * once for both user-mode and system builds.
 202  */
 203 static Property cpu_common_props[] = {
 204 #ifdef CONFIG_USER_ONLY
 205     /*
 206      * Create a property for the user-only object, so users can
 207      * adjust prctl(PR_SET_UNALIGN) from the command-line.
 208      * Has no effect if the target does not support the feature.
 209      */
 210     DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
 211                      prctl_unalign_sigbus, false),
 212 #else
 213     /*
 214      * Create a memory property for softmmu CPU object, so users can
 215      * wire up its memory.  The default if no link is set up is to use
 216      * the system address space.
 217      */
 218     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 219                      MemoryRegion *),
 220 #endif
 221     DEFINE_PROP_END_OF_LIST(),
 222 };
 223
 224 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
 225 {
 226     CPUState *cpu = CPU(obj);
 227     return cpu->start_powered_off;
 228 }
 229
 230 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
 231 {
 232     CPUState *cpu = CPU(obj);
 233     cpu->start_powered_off = value;
 234 }
 235
 236 void cpu_class_init_props(DeviceClass *dc)
 237 {
 238     ObjectClass *oc = OBJECT_CLASS(dc);
 239
 240     device_class_set_props(dc, cpu_common_props);
 241     /*
 242      * We can't use DEFINE_PROP_BOOL in the Property array for this
 243      * property, because we want this to be settable after realize.
 244      */
 245     object_class_property_add_bool(oc, "start-powered-off",
 246                                    cpu_get_start_powered_off,
 247                                    cpu_set_start_powered_off);
 248 }
 249
 250 void cpu_exec_initfn(CPUState *cpu)
 251 {
 252     cpu->as = NULL;
 253     cpu->num_ases = 0;
 254
 255 #ifndef CONFIG_USER_ONLY
 256     cpu->thread_id = qemu_get_thread_id();
 257     cpu->memory = get_system_memory();
 258     object_ref(OBJECT(cpu->memory));
 259 #endif
 260 }
 261
 262 const char *parse_cpu_option(const char *cpu_option)
 263 {
 264     ObjectClass *oc;
 265     CPUClass *cc;
 266     gchar **model_pieces;
 267     const char *cpu_type;
 268
 269     model_pieces = g_strsplit(cpu_option, ",", 2);
 270     if (!model_pieces[0]) {
 271         error_report("-cpu option cannot be empty");
 272         exit(1);
 273     }
 274
 275     oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
 276     if (oc == NULL) {
 277         error_report("unable to find CPU model '%s'", model_pieces[0]);
 278         g_strfreev(model_pieces);
 279         exit(EXIT_FAILURE);
 280     }
 281
 282     cpu_type = object_class_get_name(oc);
 283     cc = CPU_CLASS(oc);
 284     cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
 285     g_strfreev(model_pieces);
 286     return cpu_type;
 287 }
 288
 289 void list_cpus(void)
 290 {
 291     /* XXX: implement xxx_cpu_list for targets that still miss it */
 292 #if defined(cpu_list)
 293     cpu_list();
 294 #endif
 295 }
 296
 297 #if defined(CONFIG_USER_ONLY)
 298 void tb_invalidate_phys_addr(hwaddr addr)
 299 {
 300     mmap_lock();
 301     tb_invalidate_phys_page(addr);
 302     mmap_unlock();
 303 }
 304 #else
 305 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 306 {
 307     ram_addr_t ram_addr;
 308     MemoryRegion *mr;
 309     hwaddr l = 1;
 310
 311     if (!tcg_enabled()) {
 312         return;
 313     }
 314
 315     RCU_READ_LOCK_GUARD();
 316     mr = address_space_translate(as, addr, &addr, &l, false, attrs);
 317     if (!(memory_region_is_ram(mr)
 318           || memory_region_is_romd(mr))) {
 319         return;
 320     }
 321     ram_addr = memory_region_get_ram_addr(mr) + addr;
 322     tb_invalidate_phys_page(ram_addr);
 323 }
 324 #endif
 325
 326 /* enable or disable single step mode. EXCP_DEBUG is returned by the
 327    CPU loop after each instruction */
 328 void cpu_single_step(CPUState *cpu, int enabled)
 329 {
 330     if (cpu->singlestep_enabled != enabled) {
 331         cpu->singlestep_enabled = enabled;
 332
 333 #if !defined(CONFIG_USER_ONLY)
 334         const AccelOpsClass *ops = cpus_get_accel();
 335         if (ops->update_guest_debug) {
 336             ops->update_guest_debug(cpu);
 337         }
 338 #endif
 339
 340         trace_breakpoint_singlestep(cpu->cpu_index, enabled);
 341     }
 342 }
 343
 344 void cpu_abort(CPUState *cpu, const char *fmt, ...)
 345 {
 346     va_list ap;
 347     va_list ap2;
 348
 349     va_start(ap, fmt);
 350     va_copy(ap2, ap);
 351     fprintf(stderr, "qemu: fatal: ");
 352     vfprintf(stderr, fmt, ap);
 353     fprintf(stderr, "\n");
 354     cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 355     if (qemu_log_separate()) {
 356         FILE *logfile = qemu_log_trylock();
 357         if (logfile) {
 358             fprintf(logfile, "qemu: fatal: ");
 359             vfprintf(logfile, fmt, ap2);
 360             fprintf(logfile, "\n");
 361             cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 362             qemu_log_unlock(logfile);
 363         }
 364     }
 365     va_end(ap2);
 366     va_end(ap);
 367     replay_finish();
 368 #if defined(CONFIG_USER_ONLY)
 369     {
 370         struct sigaction act;
 371         sigfillset(&act.sa_mask);
 372         act.sa_handler = SIG_DFL;
 373         act.sa_flags = 0;
 374         sigaction(SIGABRT, &act, NULL);
 375     }
 376 #endif
 377     abort();
 378 }
 379
 380 /* physical memory access (slow version, mainly for debug) */
 381 #if defined(CONFIG_USER_ONLY)
 382 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 383                         void *ptr, size_t len, bool is_write)
 384 {
 385     int flags;
 386     vaddr l, page;
 387     void * p;
 388     uint8_t *buf = ptr;
 389
 390     while (len > 0) {
 391         page = addr & TARGET_PAGE_MASK;
 392         l = (page + TARGET_PAGE_SIZE) - addr;
 393         if (l > len)
 394             l = len;
 395         flags = page_get_flags(page);
 396         if (!(flags & PAGE_VALID))
 397             return -1;
 398         if (is_write) {
 399             if (!(flags & PAGE_WRITE))
 400                 return -1;
 401             /* XXX: this code should not depend on lock_user */
 402             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
 403                 return -1;
 404             memcpy(p, buf, l);
 405             unlock_user(p, addr, l);
 406         } else {
 407             if (!(flags & PAGE_READ))
 408                 return -1;
 409             /* XXX: this code should not depend on lock_user */
 410             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
 411                 return -1;
 412             memcpy(buf, p, l);
 413             unlock_user(p, addr, 0);
 414         }
 415         len -= l;
 416         buf += l;
 417         addr += l;
 418     }
 419     return 0;
 420 }
 421 #endif
 422
 423 bool target_words_bigendian(void)
 424 {
 425     return TARGET_BIG_ENDIAN;
 426 }
 427
 428 const char *target_name(void)
 429 {
 430     return TARGET_NAME;
 431 }
 432
 433 void page_size_init(void)
 434 {
 435     /* NOTE: we can always suppose that qemu_host_page_size >=
 436        TARGET_PAGE_SIZE */
 437     if (qemu_host_page_size == 0) {
 438         qemu_host_page_size = qemu_real_host_page_size();
 439     }
 440     if (qemu_host_page_size < TARGET_PAGE_SIZE) {
 441         qemu_host_page_size = TARGET_PAGE_SIZE;
 442     }
 443     qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
 444 }