hw/mips/cps.c

   1 /*
   2  * Coherent Processing System emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/module.h"
  23 #include "hw/mips/cps.h"
  24 #include "hw/mips/mips.h"
  25 #include "hw/qdev-clock.h"
  26 #include "hw/qdev-properties.h"
  27 #include "sysemu/kvm.h"
  28 #include "sysemu/reset.h"
  29
  30 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
  31 {
  32     assert(pin_number < s->num_irq);
  33     return s->gic.irq_state[pin_number].irq;
  34 }
  35
  36 static void mips_cps_init(Object *obj)
  37 {
  38     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  39     MIPSCPSState *s = MIPS_CPS(obj);
  40
  41     s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0);
  42     /*
  43      * Cover entire address space as there do not seem to be any
  44      * constraints for the base address of CPC and GIC.
  45      */
  46     memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
  47     sysbus_init_mmio(sbd, &s->container);
  48 }
  49
  50 static void main_cpu_reset(void *opaque)
  51 {
  52     MIPSCPU *cpu = opaque;
  53     CPUState *cs = CPU(cpu);
  54
  55     cpu_reset(cs);
  56 }
  57
  58 static bool cpu_mips_itu_supported(CPUMIPSState *env)
  59 {
  60     bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
  61
  62     return is_mt && !kvm_enabled();
  63 }
  64
  65 static void mips_cps_realize(DeviceState *dev, Error **errp)
  66 {
  67     MIPSCPSState *s = MIPS_CPS(dev);
  68     target_ulong gcr_base;
  69     bool itu_present = false;
  70
  71     if (!clock_get(s->clock)) {
  72         error_setg(errp, "CPS input clock is not connected to an output clock");
  73         return;
  74     }
  75
  76     for (int i = 0; i < s->num_vp; i++) {
  77         MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
  78         CPUMIPSState *env = &cpu->env;
  79
  80         /* All VPs are halted on reset. Leave powering up to CPC. */
  81         if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
  82                                       errp)) {
  83             return;
  84         }
  85         /* All cores use the same clock tree */
  86         qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
  87
  88         if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
  89             return;
  90         }
  91
  92         /* Init internal devices */
  93         cpu_mips_irq_init_cpu(cpu);
  94         cpu_mips_clock_init(cpu);
  95
  96         if (cpu_mips_itu_supported(env)) {
  97             itu_present = true;
  98             /* Attach ITC Tag to the VP */
  99             env->itc_tag = mips_itu_get_tag_region(&s->itu);
 100             env->itu = &s->itu;
 101         }
 102         qemu_register_reset(main_cpu_reset, cpu);
 103     }
 104
 105     /* Inter-Thread Communication Unit */
 106     if (itu_present) {
 107         object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
 108         object_property_set_link(OBJECT(&s->itu), "cpu[0]",
 109                                  OBJECT(first_cpu), &error_abort);
 110         object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
 111                                 &error_abort);
 112         object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
 113                                 &error_abort);
 114         if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
 115             return;
 116         }
 117
 118         memory_region_add_subregion(&s->container, 0,
 119                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
 120     }
 121
 122     /* Cluster Power Controller */
 123     object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
 124     object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp,
 125                             &error_abort);
 126     object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
 127                             &error_abort);
 128     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
 129         return;
 130     }
 131
 132     memory_region_add_subregion(&s->container, 0,
 133                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
 134
 135     /* Global Interrupt Controller */
 136     object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
 137     object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp,
 138                             &error_abort);
 139     object_property_set_uint(OBJECT(&s->gic), "num-irq", 128,
 140                             &error_abort);
 141     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
 142         return;
 143     }
 144
 145     memory_region_add_subregion(&s->container, 0,
 146                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 147
 148     /* Global Configuration Registers */
 149     gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
 150
 151     object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
 152     object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
 153                             &error_abort);
 154     object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
 155                             &error_abort);
 156     object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
 157                             &error_abort);
 158     object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
 159                              &error_abort);
 160     object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
 161                              &error_abort);
 162     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
 163         return;
 164     }
 165
 166     memory_region_add_subregion(&s->container, gcr_base,
 167                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 168 }
 169
 170 static Property mips_cps_properties[] = {
 171     DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
 172     DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
 173     DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
 174     DEFINE_PROP_END_OF_LIST()
 175 };
 176
 177 static void mips_cps_class_init(ObjectClass *klass, void *data)
 178 {
 179     DeviceClass *dc = DEVICE_CLASS(klass);
 180
 181     dc->realize = mips_cps_realize;
 182     device_class_set_props(dc, mips_cps_properties);
 183 }
 184
 185 static const TypeInfo mips_cps_info = {
 186     .name = TYPE_MIPS_CPS,
 187     .parent = TYPE_SYS_BUS_DEVICE,
 188     .instance_size = sizeof(MIPSCPSState),
 189     .instance_init = mips_cps_init,
 190     .class_init = mips_cps_class_init,
 191 };
 192
 193 static void mips_cps_register_types(void)
 194 {
 195     type_register_static(&mips_cps_info);
 196 }
 197
 198 type_init(mips_cps_register_types)