target/i386/helper.c

   1 /*
   2  *  i386 helpers (without register variable usage)
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/qapi-events-run-state.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "sysemu/runstate.h"
  25 #ifndef CONFIG_USER_ONLY
  26 #include "sysemu/hw_accel.h"
  27 #include "monitor/monitor.h"
  28 #include "kvm/kvm_i386.h"
  29 #endif
  30 #include "qemu/log.h"
  31 #ifdef CONFIG_TCG
  32 #include "tcg/insn-start-words.h"
  33 #endif
  34
  35 void cpu_sync_avx_hflag(CPUX86State *env)
  36 {
  37     if ((env->cr[4] & CR4_OSXSAVE_MASK)
  38         && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
  39             == (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
  40         env->hflags |= HF_AVX_EN_MASK;
  41     } else{
  42         env->hflags &= ~HF_AVX_EN_MASK;
  43     }
  44 }
  45
  46 void cpu_sync_bndcs_hflags(CPUX86State *env)
  47 {
  48     uint32_t hflags = env->hflags;
  49     uint32_t hflags2 = env->hflags2;
  50     uint32_t bndcsr;
  51
  52     if ((hflags & HF_CPL_MASK) == 3) {
  53         bndcsr = env->bndcs_regs.cfgu;
  54     } else {
  55         bndcsr = env->msr_bndcfgs;
  56     }
  57
  58     if ((env->cr[4] & CR4_OSXSAVE_MASK)
  59         && (env->xcr0 & XSTATE_BNDCSR_MASK)
  60         && (bndcsr & BNDCFG_ENABLE)) {
  61         hflags |= HF_MPX_EN_MASK;
  62     } else {
  63         hflags &= ~HF_MPX_EN_MASK;
  64     }
  65
  66     if (bndcsr & BNDCFG_BNDPRESERVE) {
  67         hflags2 |= HF2_MPX_PR_MASK;
  68     } else {
  69         hflags2 &= ~HF2_MPX_PR_MASK;
  70     }
  71
  72     env->hflags = hflags;
  73     env->hflags2 = hflags2;
  74 }
  75
  76 static void cpu_x86_version(CPUX86State *env, int *family, int *model)
  77 {
  78     int cpuver = env->cpuid_version;
  79
  80     if (family == NULL || model == NULL) {
  81         return;
  82     }
  83
  84     *family = (cpuver >> 8) & 0x0f;
  85     *model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
  86 }
  87
  88 /* Broadcast MCA signal for processor version 06H_EH and above */
  89 int cpu_x86_support_mca_broadcast(CPUX86State *env)
  90 {
  91     int family = 0;
  92     int model = 0;
  93
  94     if (IS_AMD_CPU(env)) {
  95         return 0;
  96     }
  97
  98     cpu_x86_version(env, &family, &model);
  99     if ((family == 6 && model >= 14) || family > 6) {
 100         return 1;
 101     }
 102
 103     return 0;
 104 }
 105
 106 /***********************************************************/
 107 /* x86 mmu */
 108 /* XXX: add PGE support */
 109
 110 void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
 111 {
 112     CPUX86State *env = &cpu->env;
 113
 114     a20_state = (a20_state != 0);
 115     if (a20_state != ((env->a20_mask >> 20) & 1)) {
 116         CPUState *cs = CPU(cpu);
 117
 118         qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
 119         /* if the cpu is currently executing code, we must unlink it and
 120            all the potentially executing TB */
 121         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 122
 123         /* when a20 is changed, all the MMU mappings are invalid, so
 124            we must flush everything */
 125         tlb_flush(cs);
 126         env->a20_mask = ~(1 << 20) | (a20_state << 20);
 127     }
 128 }
 129
 130 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
 131 {
 132     X86CPU *cpu = env_archcpu(env);
 133     int pe_state;
 134
 135     qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
 136     if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
 137         (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
 138         tlb_flush(CPU(cpu));
 139     }
 140
 141 #ifdef TARGET_X86_64
 142     if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
 143         (env->efer & MSR_EFER_LME)) {
 144         /* enter in long mode */
 145         /* XXX: generate an exception */
 146         if (!(env->cr[4] & CR4_PAE_MASK))
 147             return;
 148         env->efer |= MSR_EFER_LMA;
 149         env->hflags |= HF_LMA_MASK;
 150     } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
 151                (env->efer & MSR_EFER_LMA)) {
 152         /* exit long mode */
 153         env->efer &= ~MSR_EFER_LMA;
 154         env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
 155         env->eip &= 0xffffffff;
 156     }
 157 #endif
 158     env->cr[0] = new_cr0 | CR0_ET_MASK;
 159
 160     /* update PE flag in hidden flags */
 161     pe_state = (env->cr[0] & CR0_PE_MASK);
 162     env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
 163     /* ensure that ADDSEG is always set in real mode */
 164     env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
 165     /* update FPU flags */
 166     env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
 167         ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
 168 }
 169
 170 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
 171    the PDPT */
 172 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
 173 {
 174     env->cr[3] = new_cr3;
 175     if (env->cr[0] & CR0_PG_MASK) {
 176         qemu_log_mask(CPU_LOG_MMU,
 177                         "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
 178         tlb_flush(env_cpu(env));
 179     }
 180 }
 181
 182 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
 183 {
 184     uint32_t hflags;
 185
 186 #if defined(DEBUG_MMU)
 187     printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
 188 #endif
 189     if ((new_cr4 ^ env->cr[4]) &
 190         (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
 191          CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
 192         tlb_flush(env_cpu(env));
 193     }
 194
 195     /* Clear bits we're going to recompute.  */
 196     hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK);
 197
 198     /* SSE handling */
 199     if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
 200         new_cr4 &= ~CR4_OSFXSR_MASK;
 201     }
 202     if (new_cr4 & CR4_OSFXSR_MASK) {
 203         hflags |= HF_OSFXSR_MASK;
 204     }
 205
 206     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
 207         new_cr4 &= ~CR4_SMAP_MASK;
 208     }
 209     if (new_cr4 & CR4_SMAP_MASK) {
 210         hflags |= HF_SMAP_MASK;
 211     }
 212     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
 213         new_cr4 &= ~CR4_UMIP_MASK;
 214     }
 215     if (new_cr4 & CR4_UMIP_MASK) {
 216         hflags |= HF_UMIP_MASK;
 217     }
 218
 219     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
 220         new_cr4 &= ~CR4_PKE_MASK;
 221     }
 222     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
 223         new_cr4 &= ~CR4_PKS_MASK;
 224     }
 225
 226     if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
 227         new_cr4 &= ~CR4_LAM_SUP_MASK;
 228     }
 229
 230     env->cr[4] = new_cr4;
 231     env->hflags = hflags;
 232
 233     cpu_sync_bndcs_hflags(env);
 234     cpu_sync_avx_hflag(env);
 235 }
 236
 237 #if !defined(CONFIG_USER_ONLY)
 238 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
 239                                          MemTxAttrs *attrs)
 240 {
 241     X86CPU *cpu = X86_CPU(cs);
 242     CPUX86State *env = &cpu->env;
 243     target_ulong pde_addr, pte_addr;
 244     uint64_t pte;
 245     int32_t a20_mask;
 246     uint32_t page_offset;
 247     int page_size;
 248
 249     *attrs = cpu_get_mem_attrs(env);
 250
 251     a20_mask = x86_get_a20_mask(env);
 252     if (!(env->cr[0] & CR0_PG_MASK)) {
 253         pte = addr & a20_mask;
 254         page_size = 4096;
 255     } else if (env->cr[4] & CR4_PAE_MASK) {
 256         target_ulong pdpe_addr;
 257         uint64_t pde, pdpe;
 258
 259 #ifdef TARGET_X86_64
 260         if (env->hflags & HF_LMA_MASK) {
 261             bool la57 = env->cr[4] & CR4_LA57_MASK;
 262             uint64_t pml5e_addr, pml5e;
 263             uint64_t pml4e_addr, pml4e;
 264             int32_t sext;
 265
 266             /* test virtual address sign extension */
 267             sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
 268             if (sext != 0 && sext != -1) {
 269                 return -1;
 270             }
 271
 272             if (la57) {
 273                 pml5e_addr = ((env->cr[3] & ~0xfff) +
 274                         (((addr >> 48) & 0x1ff) << 3)) & a20_mask;
 275                 pml5e = x86_ldq_phys(cs, pml5e_addr);
 276                 if (!(pml5e & PG_PRESENT_MASK)) {
 277                     return -1;
 278                 }
 279             } else {
 280                 pml5e = env->cr[3];
 281             }
 282
 283             pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
 284                     (((addr >> 39) & 0x1ff) << 3)) & a20_mask;
 285             pml4e = x86_ldq_phys(cs, pml4e_addr);
 286             if (!(pml4e & PG_PRESENT_MASK)) {
 287                 return -1;
 288             }
 289             pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
 290                          (((addr >> 30) & 0x1ff) << 3)) & a20_mask;
 291             pdpe = x86_ldq_phys(cs, pdpe_addr);
 292             if (!(pdpe & PG_PRESENT_MASK)) {
 293                 return -1;
 294             }
 295             if (pdpe & PG_PSE_MASK) {
 296                 page_size = 1024 * 1024 * 1024;
 297                 pte = pdpe;
 298                 goto out;
 299             }
 300
 301         } else
 302 #endif
 303         {
 304             pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
 305                 a20_mask;
 306             pdpe = x86_ldq_phys(cs, pdpe_addr);
 307             if (!(pdpe & PG_PRESENT_MASK))
 308                 return -1;
 309         }
 310
 311         pde_addr = ((pdpe & PG_ADDRESS_MASK) +
 312                     (((addr >> 21) & 0x1ff) << 3)) & a20_mask;
 313         pde = x86_ldq_phys(cs, pde_addr);
 314         if (!(pde & PG_PRESENT_MASK)) {
 315             return -1;
 316         }
 317         if (pde & PG_PSE_MASK) {
 318             /* 2 MB page */
 319             page_size = 2048 * 1024;
 320             pte = pde;
 321         } else {
 322             /* 4 KB page */
 323             pte_addr = ((pde & PG_ADDRESS_MASK) +
 324                         (((addr >> 12) & 0x1ff) << 3)) & a20_mask;
 325             page_size = 4096;
 326             pte = x86_ldq_phys(cs, pte_addr);
 327         }
 328         if (!(pte & PG_PRESENT_MASK)) {
 329             return -1;
 330         }
 331     } else {
 332         uint32_t pde;
 333
 334         /* page directory entry */
 335         pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
 336         pde = x86_ldl_phys(cs, pde_addr);
 337         if (!(pde & PG_PRESENT_MASK))
 338             return -1;
 339         if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
 340             pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
 341             page_size = 4096 * 1024;
 342         } else {
 343             /* page directory entry */
 344             pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
 345             pte = x86_ldl_phys(cs, pte_addr);
 346             if (!(pte & PG_PRESENT_MASK)) {
 347                 return -1;
 348             }
 349             page_size = 4096;
 350         }
 351         pte = pte & a20_mask;
 352     }
 353
 354 #ifdef TARGET_X86_64
 355 out:
 356 #endif
 357     pte &= PG_ADDRESS_MASK & ~(page_size - 1);
 358     page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
 359     return pte | page_offset;
 360 }
 361
 362 typedef struct MCEInjectionParams {
 363     Monitor *mon;
 364     int bank;
 365     uint64_t status;
 366     uint64_t mcg_status;
 367     uint64_t addr;
 368     uint64_t misc;
 369     int flags;
 370 } MCEInjectionParams;
 371
 372 static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
 373                                       bool recursive)
 374 {
 375     MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
 376
 377     qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
 378                                    &mff);
 379 }
 380
 381 static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
 382 {
 383     MCEInjectionParams *params = data.host_ptr;
 384     X86CPU *cpu = X86_CPU(cs);
 385     CPUX86State *cenv = &cpu->env;
 386     uint64_t *banks = cenv->mce_banks + 4 * params->bank;
 387     g_autofree char *msg = NULL;
 388     bool need_reset = false;
 389     bool recursive;
 390     bool ar = !!(params->status & MCI_STATUS_AR);
 391
 392     cpu_synchronize_state(cs);
 393     recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
 394
 395     /*
 396      * If there is an MCE exception being processed, ignore this SRAO MCE
 397      * unless unconditional injection was requested.
 398      */
 399     if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
 400         emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
 401         return;
 402     }
 403
 404     if (params->status & MCI_STATUS_UC) {
 405         /*
 406          * if MSR_MCG_CTL is not all 1s, the uncorrected error
 407          * reporting is disabled
 408          */
 409         if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
 410             monitor_printf(params->mon,
 411                            "CPU %d: Uncorrected error reporting disabled\n",
 412                            cs->cpu_index);
 413             return;
 414         }
 415
 416         /*
 417          * if MSR_MCi_CTL is not all 1s, the uncorrected error
 418          * reporting is disabled for the bank
 419          */
 420         if (banks[0] != ~(uint64_t)0) {
 421             monitor_printf(params->mon,
 422                            "CPU %d: Uncorrected error reporting disabled for"
 423                            " bank %d\n",
 424                            cs->cpu_index, params->bank);
 425             return;
 426         }
 427
 428         if (!(cenv->cr[4] & CR4_MCE_MASK)) {
 429             need_reset = true;
 430             msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
 431                                   "raising triple fault", cs->cpu_index);
 432         } else if (recursive) {
 433             need_reset = true;
 434             msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
 435                                   "raising triple fault", cs->cpu_index);
 436         }
 437
 438         if (need_reset) {
 439             emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar,
 440                                       recursive);
 441             monitor_printf(params->mon, "%s", msg);
 442             qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
 443             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 444             return;
 445         }
 446
 447         if (banks[1] & MCI_STATUS_VAL) {
 448             params->status |= MCI_STATUS_OVER;
 449         }
 450         banks[2] = params->addr;
 451         banks[3] = params->misc;
 452         cenv->mcg_status = params->mcg_status;
 453         banks[1] = params->status;
 454         cpu_interrupt(cs, CPU_INTERRUPT_MCE);
 455     } else if (!(banks[1] & MCI_STATUS_VAL)
 456                || !(banks[1] & MCI_STATUS_UC)) {
 457         if (banks[1] & MCI_STATUS_VAL) {
 458             params->status |= MCI_STATUS_OVER;
 459         }
 460         banks[2] = params->addr;
 461         banks[3] = params->misc;
 462         banks[1] = params->status;
 463     } else {
 464         banks[1] |= MCI_STATUS_OVER;
 465     }
 466
 467     emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
 468 }
 469
 470 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
 471                         uint64_t status, uint64_t mcg_status, uint64_t addr,
 472                         uint64_t misc, int flags)
 473 {
 474     CPUState *cs = CPU(cpu);
 475     CPUX86State *cenv = &cpu->env;
 476     MCEInjectionParams params = {
 477         .mon = mon,
 478         .bank = bank,
 479         .status = status,
 480         .mcg_status = mcg_status,
 481         .addr = addr,
 482         .misc = misc,
 483         .flags = flags,
 484     };
 485     unsigned bank_num = cenv->mcg_cap & 0xff;
 486
 487     if (!cenv->mcg_cap) {
 488         monitor_printf(mon, "MCE injection not supported\n");
 489         return;
 490     }
 491     if (bank >= bank_num) {
 492         monitor_printf(mon, "Invalid MCE bank number\n");
 493         return;
 494     }
 495     if (!(status & MCI_STATUS_VAL)) {
 496         monitor_printf(mon, "Invalid MCE status code\n");
 497         return;
 498     }
 499     if ((flags & MCE_INJECT_BROADCAST)
 500         && !cpu_x86_support_mca_broadcast(cenv)) {
 501         monitor_printf(mon, "Guest CPU does not support MCA broadcast\n");
 502         return;
 503     }
 504
 505     run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
 506     if (flags & MCE_INJECT_BROADCAST) {
 507         CPUState *other_cs;
 508
 509         params.bank = 1;
 510         params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
 511         params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
 512         params.addr = 0;
 513         params.misc = 0;
 514         CPU_FOREACH(other_cs) {
 515             if (other_cs == cs) {
 516                 continue;
 517             }
 518             run_on_cpu(other_cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
 519         }
 520     }
 521 }
 522
 523 static inline target_ulong get_memio_eip(CPUX86State *env)
 524 {
 525 #ifdef CONFIG_TCG
 526     uint64_t data[TARGET_INSN_START_WORDS];
 527     CPUState *cs = env_cpu(env);
 528
 529     if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
 530         return env->eip;
 531     }
 532
 533     /* Per x86_restore_state_to_opc. */
 534     if (tcg_cflags_has(cs, CF_PCREL)) {
 535         return (env->eip & TARGET_PAGE_MASK) | data[0];
 536     } else {
 537         return data[0] - env->segs[R_CS].base;
 538     }
 539 #else
 540     qemu_build_not_reached();
 541 #endif
 542 }
 543
 544 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
 545 {
 546     X86CPU *cpu = env_archcpu(env);
 547     CPUState *cs = env_cpu(env);
 548
 549     if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) {
 550         env->tpr_access_type = access;
 551
 552         cpu_interrupt(cs, CPU_INTERRUPT_TPR);
 553     } else if (tcg_enabled()) {
 554         target_ulong eip = get_memio_eip(env);
 555
 556         apic_handle_tpr_access_report(cpu->apic_state, eip, access);
 557     }
 558 }
 559 #endif /* !CONFIG_USER_ONLY */
 560
 561 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 562                             target_ulong *base, unsigned int *limit,
 563                             unsigned int *flags)
 564 {
 565     CPUState *cs = env_cpu(env);
 566     SegmentCache *dt;
 567     target_ulong ptr;
 568     uint32_t e1, e2;
 569     int index;
 570
 571     if (selector & 0x4)
 572         dt = &env->ldt;
 573     else
 574         dt = &env->gdt;
 575     index = selector & ~7;
 576     ptr = dt->base + index;
 577     if ((index + 7) > dt->limit
 578         || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
 579         || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
 580         return 0;
 581
 582     *base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
 583     *limit = (e1 & 0xffff) | (e2 & 0x000f0000);
 584     if (e2 & DESC_G_MASK)
 585         *limit = (*limit << 12) | 0xfff;
 586     *flags = e2;
 587
 588     return 1;
 589 }
 590
 591 void do_cpu_init(X86CPU *cpu)
 592 {
 593 #if !defined(CONFIG_USER_ONLY)
 594     CPUState *cs = CPU(cpu);
 595     CPUX86State *env = &cpu->env;
 596     CPUX86State *save = g_new(CPUX86State, 1);
 597     int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
 598
 599     *save = *env;
 600
 601     cpu_reset(cs);
 602     cs->interrupt_request = sipi;
 603     memcpy(&env->start_init_save, &save->start_init_save,
 604            offsetof(CPUX86State, end_init_save) -
 605            offsetof(CPUX86State, start_init_save));
 606     g_free(save);
 607
 608     if (kvm_enabled()) {
 609         kvm_arch_do_init_vcpu(cpu);
 610     }
 611     apic_init_reset(cpu->apic_state);
 612 #endif /* CONFIG_USER_ONLY */
 613 }
 614
 615 #ifndef CONFIG_USER_ONLY
 616
 617 void do_cpu_sipi(X86CPU *cpu)
 618 {
 619     apic_sipi(cpu->apic_state);
 620 }
 621
 622 void cpu_load_efer(CPUX86State *env, uint64_t val)
 623 {
 624     env->efer = val;
 625     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
 626     if (env->efer & MSR_EFER_LMA) {
 627         env->hflags |= HF_LMA_MASK;
 628     }
 629     if (env->efer & MSR_EFER_SVME) {
 630         env->hflags |= HF_SVME_MASK;
 631     }
 632 }
 633
 634 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
 635 {
 636     X86CPU *cpu = X86_CPU(cs);
 637     CPUX86State *env = &cpu->env;
 638     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 639     AddressSpace *as = cpu_addressspace(cs, attrs);
 640
 641     return address_space_ldub(as, addr, attrs, NULL);
 642 }
 643
 644 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
 645 {
 646     X86CPU *cpu = X86_CPU(cs);
 647     CPUX86State *env = &cpu->env;
 648     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 649     AddressSpace *as = cpu_addressspace(cs, attrs);
 650
 651     return address_space_lduw(as, addr, attrs, NULL);
 652 }
 653
 654 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
 655 {
 656     X86CPU *cpu = X86_CPU(cs);
 657     CPUX86State *env = &cpu->env;
 658     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 659     AddressSpace *as = cpu_addressspace(cs, attrs);
 660
 661     return address_space_ldl(as, addr, attrs, NULL);
 662 }
 663
 664 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
 665 {
 666     X86CPU *cpu = X86_CPU(cs);
 667     CPUX86State *env = &cpu->env;
 668     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 669     AddressSpace *as = cpu_addressspace(cs, attrs);
 670
 671     return address_space_ldq(as, addr, attrs, NULL);
 672 }
 673
 674 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
 675 {
 676     X86CPU *cpu = X86_CPU(cs);
 677     CPUX86State *env = &cpu->env;
 678     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 679     AddressSpace *as = cpu_addressspace(cs, attrs);
 680
 681     address_space_stb(as, addr, val, attrs, NULL);
 682 }
 683
 684 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
 685 {
 686     X86CPU *cpu = X86_CPU(cs);
 687     CPUX86State *env = &cpu->env;
 688     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 689     AddressSpace *as = cpu_addressspace(cs, attrs);
 690
 691     address_space_stl_notdirty(as, addr, val, attrs, NULL);
 692 }
 693
 694 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
 695 {
 696     X86CPU *cpu = X86_CPU(cs);
 697     CPUX86State *env = &cpu->env;
 698     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 699     AddressSpace *as = cpu_addressspace(cs, attrs);
 700
 701     address_space_stw(as, addr, val, attrs, NULL);
 702 }
 703
 704 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
 705 {
 706     X86CPU *cpu = X86_CPU(cs);
 707     CPUX86State *env = &cpu->env;
 708     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 709     AddressSpace *as = cpu_addressspace(cs, attrs);
 710
 711     address_space_stl(as, addr, val, attrs, NULL);
 712 }
 713
 714 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
 715 {
 716     X86CPU *cpu = X86_CPU(cs);
 717     CPUX86State *env = &cpu->env;
 718     MemTxAttrs attrs = cpu_get_mem_attrs(env);
 719     AddressSpace *as = cpu_addressspace(cs, attrs);
 720
 721     address_space_stq(as, addr, val, attrs, NULL);
 722 }
 723 #endif