2 * AArch32 translation, common definitions.
4 * Copyright (c) 2021 Linaro, Ltd.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARM_TRANSLATE_A32_H
21 #define TARGET_ARM_TRANSLATE_A32_H
23 /* Prototypes for autogenerated disassembler functions */
24 bool disas_m_nocp(DisasContext
*dc
, uint32_t insn
);
25 bool disas_mve(DisasContext
*dc
, uint32_t insn
);
26 bool disas_vfp(DisasContext
*s
, uint32_t insn
);
27 bool disas_vfp_uncond(DisasContext
*s
, uint32_t insn
);
28 bool disas_neon_dp(DisasContext
*s
, uint32_t insn
);
29 bool disas_neon_ls(DisasContext
*s
, uint32_t insn
);
30 bool disas_neon_shared(DisasContext
*s
, uint32_t insn
);
32 void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
);
33 void arm_gen_condlabel(DisasContext
*s
);
34 bool vfp_access_check(DisasContext
*s
);
35 bool vfp_access_check_m(DisasContext
*s
, bool skip_context_update
);
36 void read_neon_element32(TCGv_i32 dest
, int reg
, int ele
, MemOp memop
);
37 void read_neon_element64(TCGv_i64 dest
, int reg
, int ele
, MemOp memop
);
38 void write_neon_element32(TCGv_i32 src
, int reg
, int ele
, MemOp memop
);
39 void write_neon_element64(TCGv_i64 src
, int reg
, int ele
, MemOp memop
);
40 TCGv_i32
add_reg_for_lit(DisasContext
*s
, int reg
, int ofs
);
41 void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
);
42 void gen_set_condexec(DisasContext
*s
);
43 void gen_update_pc(DisasContext
*s
, target_long diff
);
44 void gen_lookup_tb(DisasContext
*s
);
45 long vfp_reg_offset(bool dp
, unsigned reg
);
46 long neon_full_reg_offset(unsigned reg
);
47 long neon_element_offset(int reg
, int element
, MemOp memop
);
48 void gen_rev16(TCGv_i32 dest
, TCGv_i32 var
);
49 void clear_eci_state(DisasContext
*s
);
50 bool mve_eci_check(DisasContext
*s
);
51 void mve_update_eci(DisasContext
*s
);
52 void mve_update_and_store_eci(DisasContext
*s
);
53 bool mve_skip_vmov(DisasContext
*s
, int vn
, int index
, int size
);
55 static inline TCGv_i32
load_cpu_offset(int offset
)
57 TCGv_i32 tmp
= tcg_temp_new_i32();
58 tcg_gen_ld_i32(tmp
, tcg_env
, offset
);
62 /* Load from a 32-bit field to a TCGv_i32 */
63 #define load_cpu_field(name) \
65 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4); \
66 load_cpu_offset(offsetof(CPUARMState, name)); \
69 /* Load from the low half of a 64-bit field to a TCGv_i32 */
70 #define load_cpu_field_low32(name) \
72 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \
73 load_cpu_offset(offsetoflow32(CPUARMState, name)); \
76 void store_cpu_offset(TCGv_i32 var
, int offset
, int size
);
78 #define store_cpu_field(val, name) \
80 QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4 \
81 && sizeof_field(CPUARMState, name) != 1); \
82 store_cpu_offset(val, offsetof(CPUARMState, name), \
83 sizeof_field(CPUARMState, name)); \
86 #define store_cpu_field_constant(val, name) \
87 store_cpu_field(tcg_constant_i32(val), name)
89 /* Create a new temporary and set it to the value of a CPU register. */
90 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
92 TCGv_i32 tmp
= tcg_temp_new_i32();
93 load_reg_var(s
, tmp
, reg
);
97 void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
);
99 void gen_aa32_ld_internal_i32(DisasContext
*s
, TCGv_i32 val
,
100 TCGv_i32 a32
, int index
, MemOp opc
);
101 void gen_aa32_st_internal_i32(DisasContext
*s
, TCGv_i32 val
,
102 TCGv_i32 a32
, int index
, MemOp opc
);
103 void gen_aa32_ld_internal_i64(DisasContext
*s
, TCGv_i64 val
,
104 TCGv_i32 a32
, int index
, MemOp opc
);
105 void gen_aa32_st_internal_i64(DisasContext
*s
, TCGv_i64 val
,
106 TCGv_i32 a32
, int index
, MemOp opc
);
107 void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
108 int index
, MemOp opc
);
109 void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
110 int index
, MemOp opc
);
111 void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
112 int index
, MemOp opc
);
113 void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
114 int index
, MemOp opc
);
116 #define DO_GEN_LD(SUFF, OPC) \
117 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
118 TCGv_i32 a32, int index) \
120 gen_aa32_ld_i32(s, val, a32, index, OPC); \
123 #define DO_GEN_ST(SUFF, OPC) \
124 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
125 TCGv_i32 a32, int index) \
127 gen_aa32_st_i32(s, val, a32, index, OPC); \
130 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
131 TCGv_i32 a32
, int index
)
133 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_UQ
);
136 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
137 TCGv_i32 a32
, int index
)
139 gen_aa32_st_i64(s
, val
, a32
, index
, MO_UQ
);
143 DO_GEN_LD(16u, MO_UW
)
144 DO_GEN_LD(32u, MO_UL
)
152 #if defined(CONFIG_USER_ONLY)
155 #define IS_USER(s) (s->user)
158 /* Set NZCV flags from the high 4 bits of var. */
159 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
161 /* Swap low and high halfwords. */
162 static inline void gen_swap_half(TCGv_i32 dest
, TCGv_i32 var
)
164 tcg_gen_rotri_i32(dest
, var
, 16);