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target/riscv/kvm: change kvm_reg_id to uint64_t
2024-01-10 Max Choutarget/riscv: The whole vector register move instructions...
Signed-off-by: Max Chou <max.chou@sifive.com>
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2024-01-10 Max Choutarget/riscv: Add vill check for whole vector register...
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choudisas/riscv: Replace TABs with space
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choudisas/riscv: Add support for vector crypto extensions
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choudisas/riscv: Add rv_codec_vror_vi for vror.vi
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choudisas/riscv: Add rv_fmt_vd_vs2_uimm format
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Move vector crypto extensions to riscv_cpu_ext...
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Expose Zvks[c|g] extnesion properties
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Add cfg properties for Zvks[c|g] extensions
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Expose Zvkn[c|g] extnesion properties
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Add cfg properties for Zvkn[c|g] extensions
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Expose Zvkb extension property
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Replace Zvbb checking by Zvkb
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Add cfg property for Zvkb extension
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Expose Zvkt extension property
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-11-07 Max Choutarget/riscv: Add cfg property for Zvkt extension
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-10-12 Max Choutarget/riscv: Fix vfwmaccbf16.vf
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-09-11 Max Choutarget/riscv: Add Zvksed ISA extension support
Signed-off-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-09-11 Max Choucrypto: Add SM4 constant parameter CK
Signed-off-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-09-11 Max Choucrypto: Create sm4_subword
Signed-off-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
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2023-06-26 Max Choutcg: Fix temporary variable in tcg_gen_gvec_andcs
Signed-off-by: Max Chou <max.chou@sifive.com>
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AR7 emulation for QEMU