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target/riscv: Fix pmp NA4 implementation
2020-07-14
Bin Meng
hw/riscv: Modify MROM s
i
z
e
t
o end a
t
0
x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n Meng
h
w
/riscv:
v
irt: Sort the SoC me
m
map table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Men
g
M
A
INTAINERS: Add
a
n e
n
try
for OpenSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifi
v
e_u: Add a dummy DDR
m
emory co
n
troller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
is
c
v: sifive
_
u: Sort the SoC me
m
map table entri
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Men
g
hw
/
riscv: sif
i
ve_u: Support
different boot source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifive: Change
SiFi
v
e E/U CPU rese
t
vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target
/
riscv: Renam
e
IBEX C
P
U
init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v
:
si
f
ive_
u
: Add a new pro
p
erty msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Me
n
g
hw/risc
v
: sifive_u:
R
en
a
me serial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
h
w
/
r
i
scv: sifive_u:
Add res
e
t functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
hw/r
i
scv: sifive_
g
pi
o
: Do
not blindly trigger o
u
tput
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifive_u:
H
o
o
k a
G
PI
O
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
ve_gpi
o
: Ad
d
a new 'ngpio' pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
hw/riscv: sifi
v
e_gpio: Clean up t
h
e
codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
M
eng
hw/risc
v
: sifive_u: Generate
d
evice
t
r
ee node for
OT
P
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv
:
sifive_u: Simplify the
GEM IRQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
h
w
/riscv: opentitan
:
Remove the
r
iscv_
p
refix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
h
w
/
r
iscv: sif
i
ve_e:
Remove the
riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
r
i
scv: Keep the CPU init rou
t
ine names cons
i
stent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
en
g
riscv: Gen
e
ralize CPU init routin
e
for the imacu
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
ri
s
cv: Generalize CPU init
r
o
utin
e
for
the gcsu
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Generalize CPU
init
routin
e
for the bas
e
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
M
eng
hw/ri
s
c
v
:
virt: Remove the riscv_ prefix
o
f
t
he machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
n
g
h
w
/
riscv: s
i
five
_
u: Re
m
ove the riscv_
p
refix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
r
iscv: Chang
e
t
h
e
defa
u
l
t
behavior if no -bios optio
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
r
i
s
c
v: Su
p
press the er
r
o
r
report for QE
M
U
t
es
t
ing
w
ith
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
Meng
ro
m
s:
o
p
ensb
i
: Upg
r
ade from
v
0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
Meng
hw
/
riscv: Gen
e
r
a
te correct "mmu-
t
ype" for 32-bit
machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
riscv/sif
i
ve_u: Add a
serial pr
o
perty to th
e
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n
M
e
n
g
gi
t
lab-ci
.
yml:
Add jobs to
build
OpenS
B
I firmware
b
inar
i
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
M
eng
r
iscv
:
sifive_u: Update BIOS_FI
L
ENAME fo
r
32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin M
e
ng
r
o
ms: open
s
bi: Ad
d
32-bit firmware
image f
o
r
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bi
n
M
e
n
g
roms: opensbi: Upgra
d
e from v0
.
5
t
o
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin M
e
ng
hw: net: cadenc
e
_gem: Fix buil
d
errors in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
B
i
n Meng
r
i
s
c
v: virt:
Allow PCI
ad
d
ress 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin
M
eng
riscv:
sifive_
u
: A
d
d ethe
r
net0 t
o
the a
l
iases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
risc
v
: hw:
Drop "clock-frequency" pro
p
erty of cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
B
i
n
Meng
riscv: S
k
ip
checki
n
g
CSR privilege
level
i
n debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
si
f
ive_u: Upd
a
te mod
e
l and compatib
l
e strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
i
f
ive_u: Remove handcr
a
ft
e
d clock nodes
for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Fix broke
n
GEM support
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
riscv: sifiv
e
_u: Instan
t
i
ate OTP
m
em
o
ry with a seri
a
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Men
g
risc
v
: s
i
five: Impleme
n
t a model for SiFiv
e
FU540
OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Me
n
g
ris
c
v
:
r
o
ms: Update default bios for sifive_u m
a
chin
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: sif
i
ve_u: Chang
e
UART node
n
ame in devic
e
tr
e
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive
_
u: U
p
d
a
te UART base ad
d
re
s
ses
and IRQ
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Reference PRC
I
clocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
r
i
sc
v
: sifive_u:
A
d
d
PRCI block
t
o the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive_u: Generat
e
hfclk and rtcclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: sifive: Imple
m
e
nt PRCI model for FU5
4
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
r
i
scv: sif
i
ve_u: U
p
d
a
te
P
LIC h
a
rt topology co
n
fi
g
uration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
eng
riscv: sifive_
u
:
Update
h
ar
t
c
onfigu
r
ation to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
ri
s
cv: sifive_u
:
S
e
t the minimum number of cpus to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
h
art:
A
dd a "hartid-base" prop
e
rty to
R
ISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: hart: Extract hart realiz
e
to a separate rou
t
in
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: Add
a
sif
i
ve_cpu
.
h to incl
u
de both E and
U
cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive_e: Drop sifiv
e
_mmio_emul
a
te()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
r
i
scv:
s
ifive_e: prci: Update the PRCI re
g
ister blo
c
k
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_e: prci: Fix a ty
p
o o
f
hfxosccfg register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
r
i
scv: sifive: Rename
sifive
_
prci
.
{c, h}
t
o s
i
five_e_p
r
ci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
r
i
scv: sifiv
e
_u: Remove th
e
unne
c
essary i
n
clu
d
e of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v: roms: Remove executable
attri
b
u
t
e of opensbi
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
ri
s
cv: h
w
:
Rem
o
ve the unnecessary include of target
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: hw: Ch
a
n
g
e to use
q
emu_
l
og_mask(LOG_GUE
S
T_
E
RROR
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: hw: Change create_fdt()
t
o return voi
d
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
r
i
scv: hw
:
Remov
e
not n
e
e
d
ed PLIC properties in d
e
vice
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: hw: Use qemu_fdt_setprop_cell()
for property
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv: hw: Remove superfluo
u
s
"
linu
x
, phandle" property
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: hw: Remove duplicated "hw/h
w
.
h" inclusio
n
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
riscv:
s
ifive_test: Add reset fun
c
tionality
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
ris
c
v: h
m
p: Add a comma
n
d t
o
show vir
t
u
al memory mappings
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
r
iscv:
R
e
s
olve fu
l
l p
a
th of th
e
g
i
ven bios ima
g
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: Add a
helper
routine
f
o
r
finding firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: rv32: Roo
t
pa
g
e table address ca
n
be la
r
ge
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-08-13
Bi
n
Meng
ri
s
c
v
: roms: Fix mak
e
rules f
o
r building sifive_u bios
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-27
Bin M
e
ng
ris
c
v: s
i
five_u: Updat
e
the plic
h
ar
t
config to support
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-27
Bin Meng
riscv:
s
ifiv
e
_
u
: Do not create hard-cod
e
d
phandles
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-24
Bin
Men
g
risc
v
: virt: Correct pci
"bus-range" encoding
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-03-19
B
i
n Meng
riscv: s
i
fi
v
e_u: Correct
UART0's I
R
Q
in the device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-03-19
Bin Meng
riscv: sifive
_
u
art: Generate TX inter
r
upt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree