2021-06-07 | Frank Chang | target/riscv: rvb: generalized or-combine Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-14-frank.chang@sifive.com |
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2021-06-07 | Frank Chang | target/riscv: rvb: generalized reverse Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-13-frank.chang@sifive.com |
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2021-06-07 | Frank Chang | target/riscv: rvb: single-bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-10-frank.chang@sifive.com |
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2021-06-07 | Frank Chang | target/riscv: add gen_shifti() and gen_shiftiw() helper... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-9-frank.chang@sifive.com |
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2021-06-07 | Frank Chang | target/riscv: rvb: count bits set Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com |
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2021-05-11 | Frank Chang | fpu/softfloat: set invalid excp flag for RISC-V muladd... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210420013150.21992-1-frank.chang@sifive.com |
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2021-05-11 | Frank Chang | target/riscv: fix vrgather macro index variable type bug Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210419060302.14075-1-frank.chang@sifive.com |
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2021-03-23 | Frank Chang | target/riscv: fix vs() to return proper error code Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210223065935.20208-1-frank.chang@sifive.com |
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2020-08-28 | Frank Chang | softfloat: Add fp16 and uint8/int8 conversion functions Signed-off-by: Frank Chang <frank.chang@sifive.com> |
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2020-07-14 | Frank Chang | target/riscv: fix vill bit index in vtype register Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> |
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2020-07-14 | Frank Chang | target/riscv: fix return value of do_opivx_widen() Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-4-frank.chang@sifive.com> |
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2020-07-14 | Frank Chang | target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-3-frank.chang@sifive.com> |
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2020-07-14 | Frank Chang | target/riscv: fix rsub gvec tcg_assert_listed_vecop... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-2-frank.chang@sifive.com> |
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