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target/riscv: rvb: generalized or-combine
2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: single-bit instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: add gen_shifti() and gen_shiftiw() helper...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: count bits set
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-05-11 Frank Changtarget/riscv: fix vrgather macro index variable type bug
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-03-23 Frank Changtarget/riscv: fix vs() to return proper error code
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-08-28 Frank Changsoftfloat: Add fp16 and uint8/int8 conversion functions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix vill bit index in vtype register
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix return value of do_opivx_widen()
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix rsub gvec tcg_assert_listed_vecop...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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AR7 emulation for QEMU