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MAINTAINERS: Change to my personal email address
2019-11-01 Palmer DabbeltMAINTAINERS: Change to my personal email address
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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2019-10-28 Palmer DabbeltRISC-V: Implement cpu_do_transaction_failed
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-10-28 Palmer DabbeltRISC-V: Handle bus errors in the page table walker
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-06-26 Palmer DabbeltRISC-V: Add support for the Zicsr extension
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-06-26 Palmer DabbeltRISC-V: Add support for the Zifencei extension
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-06-24 Palmer DabbeltRISC-V: Fix a memory leak when realizing a sifive_e
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-03-22 Palmer Dabbelttarget/riscv: Zero extend the inputs of divuw and remuw
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2019-02-11 Palmer DabbeltMAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Palmer DabbeltMAINTAINERS: Mark RISC-V as Supported
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 Palmer DabbeltRISC-V: Respect fences for user-only emulators
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-30 Palmer DabbeltAdd qemu-riscv@nongnu.org as the RISC-V list
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-30 Palmer DabbeltAdd Alistair as a RISC-V Maintainer
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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AR7 emulation for QEMU