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hw/sd: Introduce receive_ready() callback
2020-06-19
Bin
M
e
ng
hw/
r
iscv: s
i
five_u: Simplify the
GEM IRQ connect co
d
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: opentitan
:
R
em
o
ve the riscv_ prefix
o
f the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
hw/r
i
scv
:
sifive_e: Remo
v
e the riscv_ prefix
o
f the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
ris
c
v:
K
ee
p
the CPU init rou
t
ine na
m
es consistent
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
s
c
v: Gen
e
ralize CPU init routine for the
imacu CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
riscv: Gener
a
lize CPU init routine for
t
h
e gcsu CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
riscv: Generalize CPU init
r
outine for t
h
e base CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
M
eng
h
w
/
r
iscv
:
virt: R
e
m
ove
t
he riscv_ p
r
efix of the ma
c
hine
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/ri
s
cv
:
sifi
v
e_u: Remove the riscv
_
prefix o
f
the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
B
in Me
n
g
ris
c
v: Change the default beha
v
ior if
n
o
-bios option
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
ng
riscv:
Sup
p
ress t
h
e er
r
or
report for QEMU t
e
st
i
ng with
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree