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target/riscv: Correct a comment in riscv_csrrw()
2021-09-01 Bin Mengtarget/riscv: Correct a comment in riscv_csrrw()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Menghw/riscv: virt: Move flash node to root
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Vijai Kumar Khw/char: Add config for shakti uart
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the flash alias
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francischar: ibex_uart: Update the register layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Menghw/riscv: sifive_u: Make sure firmware info is 8-byte...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Menghw/riscv: sifive_u: Correct the CLINT timebase frequency
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Update Microchip Icicle Kit for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Jose Martinstarget/riscv: hardwire bits in hideleg and hedeleg
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Add documentation for virt machine
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2021-07-14 Bin Mengdocs/system: riscv: Fix CLINT name in the sifive_u doc
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2021-07-14 Bin Mengtarget/riscv: csr: Remove redundant check in fp csr...
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2021-07-14 Bin Mengtarget/riscv: pmp: Fix some typos
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2021-06-24 Alistair Francishw/riscv: OpenTitan: Connect the mtime and mtimecmp...
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2021-06-24 Alistair Francishw/timer: Initial commit of Ibex Timer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
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2021-06-24 Lukas Jüngerhw/char: QOMify sifive_uart
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2021-06-24 Lukas Jüngerhw/char: Consistent function names for sifive_uart
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2021-06-24 Bin Mengtarget/riscv: gdbstub: Fix dynamic CSR XML generation
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: add b-ext version cpu option
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2021-06-07 Kito Chengtarget/riscv: rvb: support and turn on B-extension...
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2021-06-07 Kito Chengtarget/riscv: rvb: add/shift with prefix zero-extend
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2021-06-07 Kito Chengtarget/riscv: rvb: address calculation
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2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: rotate (left/right)
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2021-06-07 Kito Chengtarget/riscv: rvb: shift ones
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2021-06-07 Frank Changtarget/riscv: rvb: single-bit instructions
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2021-06-07 Frank Changtarget/riscv: add gen_shifti() and gen_shiftiw() helper...
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2021-06-07 Kito Chengtarget/riscv: rvb: sign-extend instructions
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2021-06-07 Kito Chengtarget/riscv: rvb: min/max instructions
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2021-06-07 Kito Chengtarget/riscv: rvb: pack two words into one register
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2021-06-07 Kito Chengtarget/riscv: rvb: logic-with-negate
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2021-06-07 Frank Changtarget/riscv: rvb: count bits set
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2021-06-07 Kito Chengtarget/riscv: rvb: count leading/trailing zeros
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: reformat @sh format encoding for B-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 LIU Zhiweitarget/riscv: Pass the same value to oprsz and maxsz.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Changbin Dutarget/riscv: Dump CSR mscratch/sscratch/satp
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengtarget/riscv: Remove unnecessary riscv_*_names[] declaration
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Philippe Mathieu... target/riscv: Do not include 'pmp.h' in user emulation
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Jose Martinstarget/riscv: fix wfi exception behavior
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: microchip_pfsoc: Support direct kernel boot
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Use macros for BIOS image names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: sifive_u: Document '-dtb' usage
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: Correct the indentation level of...
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2021-06-07 Bin Menghw/riscv: Support the official PLIC DT bindings
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Support the official CLINT DT bindings
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: virt: Switch to use qemu_fdt_setprop_string_array...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
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2021-05-11 Emmanuel Blottarget/riscv: fix a typo with interrupt names
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alexander Wagnerhw/riscv: Fix OT IBEX reset vector
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Emmanuel Blottarget/riscv: fix exception index on instruction access...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changtarget/riscv: fix vrgather macro index variable type bug
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Add a config option for ePMP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Implementation of enhanced PMP (ePMP)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Add ePMP CSR access functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Define ePMP mseccfg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Kdocs: Add documentation for shakti_c machine
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 LIU Zhiweitarget/riscv: Fixup saturate subtract function
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Jade Finkriscv: don't look at SUM when accessing memory from...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Khw/riscv: Connect Shakti UART to Shakti platform
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Khw/char: Add Shakti UART emulation
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Kriscv: Add initial support for Shakti C machine
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Ktarget/riscv: Add Shakti C class CPU
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Bin Menghw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Dylan Jhongtarget/riscv: Align the data type of reset vector address
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Axel Heiderdocs/system/generic-loader.rst: Fix style
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2021-05-11 Atish Patratarget/riscv: Remove privilege v1.9 specific CSR related...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Prevent lost illegal instruction exceptions
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2021-03-23 Bin Mengdocs/system: riscv: Add documentation for 'microchip...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/riscv: microchip_pfsoc: Map EMMC/SD mux register
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/block: m25p80: Support fast read for SST flashes
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU