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target/riscv/cpu.c: create KVM mock properties
2023-07-10 Daniel Henrique... target/riscv/cpu.c: create KVM mock properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: remove priv_ver check from riscv_isa_str...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: add satp_mode properties earlier
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: add multi-letter extension KVM...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: update KVM MISA bits
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: add KVM specific MISA properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu: add misa_ext_info_arr[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: handle mvendorid/marchid/mimpid for KVM...
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2023-07-10 Daniel Henrique... target/riscv: read marchid/mimpid in kvm_riscv_init_machine_...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: use KVM scratch CPUs to init KVM properties
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'marchid' value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mimpid' value
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mvendorid' value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: skip features setup for KVM CPUs
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2023-07-10 Lakshmi Bai Raja... hw/riscv: virt: Convert fdt_load_addr to uint64_t
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2023-07-10 Guenter Roeckriscv: Generate devicetree only after machine initialization...
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2023-07-10 yang.zhangtarget/riscv KVM_RISCV_SET_TIMER macro is not configured...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add disas support for BF16 extensions
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2023-07-10 Jason Chientarget/riscv: Set the correct exception for implict...
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2023-07-10 Weiwei Litarget/riscv: Expose properties for BF16 extensions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zvfbfwma extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zvfbfmin extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zfbfmin extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add properties for BF16 extensions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Robbin Ehnlinux-user/riscv: Add syscall riscv_hwprobe
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... hw/riscv/virt: Restrict ACLINT to TCG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Ivan Klokovtarget/riscv: Add RVV registers to log
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... target/riscv: Only build KVM guest with same wordsize...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... target/riscv: Only unify 'riscv32/64' -> 'riscv' for...
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2023-07-10 Tommy Wutests/qtest: sifive-e-aon-watchdog-test.c: Add QTest...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Tommy Wuhw/riscv: sifive_e: Support the watchdog timer of HiFive...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Tommy Wuhw/misc: sifive_e_aon: Support the watchdog timer of...
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2023-07-10 Bin Mengtests/avocado: riscv: Enable 32-bit Spike OpenSBI boot...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Bin Mengroms/opensbi: Upgrade from v1.2 to v1.3
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: update cur_pmbase/pmmask based on mode...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add additional xlen for address when...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: fix veyron-v1 CPU properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Remove redundant assignment to SXL
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Support MSTATUS.MPV/GVA only when RVH...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Make MPV only work when MPP != PRV_M
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Add support for XThead* instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Add support for XVentanaCondOps
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Provide infrastructure for vendor extensions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Encapsulate opcode_data into decode
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Make rv_op_illegal a shared enum value
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2023-07-10 Christoph Müllnerdisas/riscv: Move types/constants to new header file
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnertarget/riscv: Factor out extension tests to cpu_cfg.h
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 LIU Zhiweitarget/riscv: Use xl instead of mxl for disassemble
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-14 Tommy Wuhw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfg...
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2023-06-13 Himanshu Chauhantarget/riscv: Smepmp: Return error when access permission...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: Remove the check for...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: clean up reference of...
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2023-06-13 Weiwei Litarget/riscv: Fix initialized value for cur_pmmask
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Ivan Klokovutil/log: Add vector registers to log
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Ldocs/system: riscv: Add pflash usage details
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Lriscv/virt: Support using pflash via -blockdev option
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Lhw/riscv: virt: Assume M-mode FW in pflash0 only when...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Remove pc_succ_insn from DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Enable PC-relative translation
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Use true diff for gen_pc_plus_diff
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Change gen_set_pc_imm to gen_update_pc
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Change gen_goto_tb to work on displacements
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Introduce cur_insn_len into DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Fix target address to update badaddr
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Lidisas/riscv.c: Remove redundant parentheses
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2023-06-13 Weiwei Lidisas/riscv.c: Fix lines with over 80 characters
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Lidisas/riscv.c: Remove unused decomp_rv32/64 value for...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Lidisas/riscv.c: Support disas for Z*inx extensions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Lidisas/riscv.c: Support disas for Zcm* extensions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Pass RISCVCPUConfig as target_info to...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Split RISCVCPUConfig declarations from...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Lidisas: Change type of disassemble_info.target_info...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Mayuresh Chitaletarget/riscv: smstateen knobs
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Mayuresh Chitaletarget/riscv: Reuse tb->flags.FS
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Mayuresh Chitaletarget/riscv: smstateen check for fcsr
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Update cur_pmmask/base when xl changes
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Fix pointer mask transformation for vector...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Yin Wanghw/riscv: qemu crash when NUMA nodes exceed available...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Philippe Mathieu... hw/riscv/opentitan: Correct OpenTitanState parent type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Philippe Mathieu... hw/riscv/opentitan: Explicit machine type definition
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Philippe Mathieu... hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Philippe Mathieu... hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Philippe Mathieu... hw/riscv/opentitan: Rename machine_[class]_init() functions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Deny access if access is partially inside...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB only when pmpcfg/pmpaddr really...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB when pmpaddr is updated
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Update the next rule addr in pmpaddr_csr_write()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB when MMWP or MML bits are changed
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Remove unused paramters in pmp_hart_has_privs_...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Make RLB/MML/MMWP bits writable only...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Change the return type of pmp_hart_has_privs...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Make the short cut really work in pmp_hart_has...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Move pmp_get_tlb_size apart from get_physical_...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Update pmp_get_tlb_size()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Daniel Henrique... target/riscv: rework write_misa()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Daniel Henrique... target/riscv/cpu.c: validate extensions before riscv_timer_i...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU