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hw/arm: xlnx-zynqmp: Clean up coding convention issues
2021-03-05
Rebecca
C
ran
target/a
r
m: Se
t
I
D_PFR2
.
SSBS to 1 for "max" 32-bit CP
U
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-03-05
Reb
e
cca
Cran
target
/
arm: Enable FEA
T
_
S
S
BS f
o
r
"max"
AARCH64
CP
U
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-03-05
Rebecca Cran
target/arm: Add support
for FEAT_SSBS, Speculative
.
.
.
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-02-11
Rebe
c
ca Cran
target/arm: Set ID_PFR0
.
DIT t
o
1 for "max" 32-bit CPU
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-02-11
Rebecca Cran
target/arm: Set ID_AA64P
F
R0
.
D
I
T and I
D
_PFR0
.
DI
T
t
o
.
.
.
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-02-11
Rebecca
Cran
t
a
r
g
et/arm: S
u
ppo
r
t AA3
2
D
IT by
movi
n
g PSTATE_SS
from
.
.
.
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2021-02-11
Rebec
c
a Cran
ta
r
get/arm: Add
s
up
p
o
r
t for F
E
AT_DIT, Data Inde
p
endent
.
.
.
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree
2020-11-17
Rebe
c
c
a
Cran
g
it
l
a
b-ci: Use $C
I
_REGISTRY instead of har
d
-
coding
.
.
.
Signed-off-by:
Rebecca Cran
<rebecca@nuviainc.com>
commit
|
commitdiff
|
tree