From f4349ba966abfe39f5d98694abd7c7551d5c8c02 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 6 Apr 2021 22:26:21 +0200 Subject: [PATCH] target/mips: Fix TCG temporary leak in gen_cache_operation() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Fix a TCG temporary leak when translating CACHE opcode. Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210406202857.1440744-1-f4bug@amsat.org> --- target/mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c518bf3963..71fa5ec197 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, TCGv t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); gen_helper_cache(cpu_env, t1, t0); + tcg_temp_free(t1); + tcg_temp_free_i32(t0); } #if defined(TARGET_MIPS64) -- 2.11.4.GIT