From e309dac24b51eda361bca83f1881ba53b09f4d5e Mon Sep 17 00:00:00 2001 From: Andrew Baumann Date: Fri, 15 Jan 2016 14:12:57 -0800 Subject: [PATCH] delete orig files from bad merge --- hw/arm/Makefile.objs.orig | 22 -- hw/arm/bcm2835_peripherals.c.orig | 492 ------------------------------ hw/arm/bcm2836.c.orig | 169 ---------- hw/arm/raspi.c.orig | 255 ---------------- hw/intc/bcm2835_ic.c.orig | 278 ----------------- hw/intc/bcm2836_control.c.orig | 368 ---------------------- hw/misc/Makefile.objs.orig | 53 ---- hw/misc/bcm2835_mbox.c.orig | 406 ------------------------ hw/misc/bcm2835_property.c.orig | 445 --------------------------- include/hw/arm/bcm2835_peripherals.h.orig | 74 ----- include/hw/arm/raspi_platform.h.orig | 262 ---------------- include/hw/intc/bcm2835_ic.h.orig | 45 --- include/hw/intc/bcm2836_control.h.orig | 59 ---- include/hw/misc/bcm2835_mbox.h.orig | 46 --- include/hw/misc/bcm2835_mbox_defs.h.orig | 31 -- include/hw/misc/bcm2835_property.h.orig | 43 --- 16 files changed, 3048 deletions(-) delete mode 100755 hw/arm/Makefile.objs.orig delete mode 100755 hw/arm/bcm2835_peripherals.c.orig delete mode 100644 hw/arm/bcm2836.c.orig delete mode 100644 hw/arm/raspi.c.orig delete mode 100755 hw/intc/bcm2835_ic.c.orig delete mode 100755 hw/intc/bcm2836_control.c.orig delete mode 100755 hw/misc/Makefile.objs.orig delete mode 100644 hw/misc/bcm2835_mbox.c.orig delete mode 100755 hw/misc/bcm2835_property.c.orig delete mode 100755 include/hw/arm/bcm2835_peripherals.h.orig delete mode 100755 include/hw/arm/raspi_platform.h.orig delete mode 100755 include/hw/intc/bcm2835_ic.h.orig delete mode 100755 include/hw/intc/bcm2836_control.h.orig delete mode 100644 include/hw/misc/bcm2835_mbox.h.orig delete mode 100644 include/hw/misc/bcm2835_mbox_defs.h.orig delete mode 100755 include/hw/misc/bcm2835_property.h.orig diff --git a/hw/arm/Makefile.objs.orig b/hw/arm/Makefile.objs.orig deleted file mode 100755 index 552f04b9aa..0000000000 --- a/hw/arm/Makefile.objs.orig +++ /dev/null @@ -1,22 +0,0 @@ -obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o -obj-$(CONFIG_DIGIC) += digic_boards.o -obj-y += integratorcp.o mainstone.o musicpal.o nseries.o -obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o -obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o -obj-$(CONFIG_ACPI) += virt-acpi-build.o -obj-y += netduino2.o -obj-y += sysbus-fdt.o - -obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o -obj-$(CONFIG_DIGIC) += digic.o -obj-y += omap1.o omap2.o strongarm.o -obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -<<<<<<< HEAD -obj-$(CONFIG_RASPI) += bcm2835.o bcm2835_peripherals.o bcm2836.o raspi.o -======= -obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o ->>>>>>> upstreaming-raspi -obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o -obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o -obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o -obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o diff --git a/hw/arm/bcm2835_peripherals.c.orig b/hw/arm/bcm2835_peripherals.c.orig deleted file mode 100755 index 1174f3cee0..0000000000 --- a/hw/arm/bcm2835_peripherals.c.orig +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#include "hw/arm/bcm2835_peripherals.h" -#include "hw/misc/bcm2835_mbox_defs.h" -#include "hw/arm/raspi_platform.h" - -<<<<<<< HEAD -======= -/* Peripheral base address on the VC (GPU) system bus */ -#define BCM2835_VC_PERI_BASE 0x7e000000 - ->>>>>>> upstreaming-raspi -/* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ -#define BCM2835_SDHC_CAPAREG 0x52034b4 - -static void bcm2835_peripherals_init(Object *obj) -{ - BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); - - /* Memory region for peripheral devices, which we export to our parent */ -<<<<<<< HEAD - memory_region_init_io(&s->peri_mr, OBJECT(s), NULL, s, - "bcm2835_peripherals", 0x1000000); - object_property_add_child(obj, "peripheral_io", OBJECT(&s->peri_mr), NULL); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); - - /* Internal memory region for peripheral bus addresses (not exported) */ - memory_region_init_io(&s->gpu_bus_mr, OBJECT(s), NULL, s, "bcm2835_gpu_bus", - (uint64_t)1 << 32); - object_property_add_child(obj, "gpu_bus", OBJECT(&s->gpu_bus_mr), NULL); - - /* Internal memory region for communication of mailbox channel data */ - memory_region_init_io(&s->mbox_mr, OBJECT(s), NULL, s, "bcm2835_mbox", - MBOX_CHAN_COUNT << 4); -======= - memory_region_init_io(&s->peri_mr, obj, NULL, s, "bcm2835-peripherals", - 0x1000000); - object_property_add_child(obj, "peripheral-io", OBJECT(&s->peri_mr), NULL); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); - - /* Internal memory region for peripheral bus addresses (not exported) */ - memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); - object_property_add_child(obj, "gpu-bus", OBJECT(&s->gpu_bus_mr), NULL); - - /* Internal memory region for request/response communication with - * mailbox-addressable peripherals (not exported) - */ - memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox", - MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT); ->>>>>>> upstreaming-raspi - - /* Interrupt Controller */ - object_initialize(&s->ic, sizeof(s->ic), TYPE_BCM2835_IC); - object_property_add_child(obj, "ic", OBJECT(&s->ic), NULL); - qdev_set_parent_bus(DEVICE(&s->ic), sysbus_get_default()); - - /* UART0 */ - s->uart0 = SYS_BUS_DEVICE(object_new("pl011")); - object_property_add_child(obj, "uart0", OBJECT(s->uart0), NULL); - qdev_set_parent_bus(DEVICE(s->uart0), sysbus_get_default()); - -<<<<<<< HEAD - /* AUX / UART1 */ - object_initialize(&s->aux, sizeof(s->aux), TYPE_BCM2835_AUX); - object_property_add_child(obj, "aux", OBJECT(&s->aux), NULL); - qdev_set_parent_bus(DEVICE(&s->aux), sysbus_get_default()); - - /* System timer */ - object_initialize(&s->st, sizeof(s->st), TYPE_BCM2835_ST); - object_property_add_child(obj, "systimer", OBJECT(&s->st), NULL); - qdev_set_parent_bus(DEVICE(&s->st), sysbus_get_default()); - - /* ARM timer */ - object_initialize(&s->timer, sizeof(s->timer), TYPE_BCM2835_TIMER); - object_property_add_child(obj, "armtimer", OBJECT(&s->timer), NULL); - qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); - - /* USB controller */ - object_initialize(&s->usb, sizeof(s->usb), TYPE_BCM2835_USB); - object_property_add_child(obj, "usb", OBJECT(&s->usb), NULL); - qdev_set_parent_bus(DEVICE(&s->usb), sysbus_get_default()); - - object_property_add_const_link(OBJECT(&s->usb), "dma_mr", - OBJECT(&s->gpu_bus_mr), &error_abort); - - /* MPHI - Message-based Parallel Host Interface */ - object_initialize(&s->mphi, sizeof(s->mphi), TYPE_BCM2835_MPHI); - object_property_add_child(obj, "mphi", OBJECT(&s->mphi), NULL); - qdev_set_parent_bus(DEVICE(&s->mphi), sysbus_get_default()); - -======= ->>>>>>> upstreaming-raspi - /* Mailboxes */ - object_initialize(&s->mboxes, sizeof(s->mboxes), TYPE_BCM2835_MBOX); - object_property_add_child(obj, "mbox", OBJECT(&s->mboxes), NULL); - qdev_set_parent_bus(DEVICE(&s->mboxes), sysbus_get_default()); - -<<<<<<< HEAD - object_property_add_const_link(OBJECT(&s->mboxes), "mbox_mr", - OBJECT(&s->mbox_mr), &error_abort); - - /* Power management */ - object_initialize(&s->power, sizeof(s->power), TYPE_BCM2835_POWER); - object_property_add_child(obj, "power", OBJECT(&s->power), NULL); - qdev_set_parent_bus(DEVICE(&s->power), sysbus_get_default()); - - /* Framebuffer */ - object_initialize(&s->fb, sizeof(s->fb), TYPE_BCM2835_FB); - object_property_add_child(obj, "fb", OBJECT(&s->fb), NULL); - object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size", - &error_abort); - qdev_set_parent_bus(DEVICE(&s->fb), sysbus_get_default()); - - object_property_add_const_link(OBJECT(&s->fb), "dma_mr", - OBJECT(&s->gpu_bus_mr), &error_abort); - -======= - object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr", - OBJECT(&s->mbox_mr), &error_abort); - ->>>>>>> upstreaming-raspi - /* Property channel */ - object_initialize(&s->property, sizeof(s->property), TYPE_BCM2835_PROPERTY); - object_property_add_child(obj, "property", OBJECT(&s->property), NULL); - qdev_set_parent_bus(DEVICE(&s->property), sysbus_get_default()); - -<<<<<<< HEAD - object_property_add_const_link(OBJECT(&s->property), "bcm2835_fb", - OBJECT(&s->fb), &error_abort); - object_property_add_const_link(OBJECT(&s->property), "dma_mr", -======= - object_property_add_const_link(OBJECT(&s->property), "dma-mr", ->>>>>>> upstreaming-raspi - OBJECT(&s->gpu_bus_mr), &error_abort); - - /* Extended Mass Media Controller */ - object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI); - object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL); - qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default()); -<<<<<<< HEAD - - /* DMA Channels */ - object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA); - object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL); - qdev_set_parent_bus(DEVICE(&s->dma), sysbus_get_default()); - - object_property_add_const_link(OBJECT(&s->dma), "dma_mr", - OBJECT(&s->gpu_bus_mr), &error_abort); - -======= ->>>>>>> upstreaming-raspi -} - -static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) -{ - BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); -<<<<<<< HEAD - MemoryRegion *ram; - Error *err = NULL; - uint32_t ram_size, vcram_size; - int n; - - /* Map peripherals and RAM into the GPU address space. */ - memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), - "bcm2835_peripherals", &s->peri_mr, 0, -======= - Object *obj; - MemoryRegion *ram; - Error *err = NULL; - uint32_t ram_size; - int n; - - obj = object_property_get_link(OBJECT(dev), "ram", &err); - if (obj == NULL) { - error_setg(errp, "%s: required ram link not found: %s", - __func__, error_get_pretty(err)); - return; - } - - ram = MEMORY_REGION(obj); - ram_size = memory_region_size(ram); - - /* Map peripherals and RAM into the GPU address space. */ - memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), - "bcm2835-peripherals", &s->peri_mr, 0, ->>>>>>> upstreaming-raspi - memory_region_size(&s->peri_mr)); - - memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, - &s->peri_mr_alias, 1); - -<<<<<<< HEAD - /* XXX: assume that RAM is contiguous and mapped at system address zero */ - ram = memory_region_find(get_system_memory(), 0, 1).mr; - assert(ram != NULL && memory_region_size(ram) >= 128 * 1024 * 1024); - ram_size = memory_region_size(ram); - - /* RAM is aliased four times (different cache configurations) on the GPU */ - for (n = 0; n < 4; n++) { - memory_region_init_alias(&s->ram_alias[n], OBJECT(s), - "bcm2835_gpu_ram_alias[*]", ram, 0, ram_size); -======= - /* RAM is aliased four times (different cache configurations) on the GPU */ - for (n = 0; n < 4; n++) { - memory_region_init_alias(&s->ram_alias[n], OBJECT(s), - "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); ->>>>>>> upstreaming-raspi - memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, - &s->ram_alias[n], 0); - } - - /* Interrupt Controller */ - object_property_set_bool(OBJECT(&s->ic), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); - sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); - - /* UART0 */ - object_property_set_bool(OBJECT(s->uart0), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, - sysbus_mmio_get_region(s->uart0, 0)); - sysbus_connect_irq(s->uart0, 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, -<<<<<<< HEAD - INTERRUPT_VC_UART)); - - /* AUX / UART1 */ - object_property_set_bool(OBJECT(&s->aux), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_AUX)); - - /* System timer */ - object_property_set_bool(OBJECT(&s->st), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, ST_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->st), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_TIMER0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 1, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_TIMER1)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 2, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_TIMER2)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 3, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_TIMER3)); - - /* ARM timer */ - object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, ARMCTRL_TIMER0_1_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, - INTERRUPT_ARM_TIMER - ARM_IRQ0_BASE)); /* XXX */ - - /* USB controller */ - object_property_set_bool(OBJECT(&s->usb), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, USB_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->usb), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_VC_USB)); - - /* MPHI - Message-based Parallel Host Interface */ - object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, - INTERRUPT_HOSTPORT)); -======= - INTERRUPT_UART)); ->>>>>>> upstreaming-raspi - - /* Mailboxes */ - object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, -<<<<<<< HEAD - INTERRUPT_ARM_MAILBOX - ARM_IRQ0_BASE)); - - /* Mailbox-addressable peripherals use the private mbox_mr address space - * and pseudo-irqs to dispatch requests and responses. */ - - /* Power management */ - object_property_set_bool(OBJECT(&s->power), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_POWER << MBOX_AS_CHAN_SHIFT, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->power), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->power), 0, - qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_POWER)); - - /* Framebuffer */ - vcram_size = (uint32_t)object_property_get_int(OBJECT(s), "vcram-size", - &err); - if (err) { - error_propagate(errp, err); - return; - } - - object_property_set_int(OBJECT(&s->fb), ram_size - vcram_size, - "vcram-base", &err); - if (err) { - error_propagate(errp, err); - return; - } - - object_property_set_bool(OBJECT(&s->fb), true, "realized", &err); -======= - INTERRUPT_ARM_MAILBOX)); - - /* Property channel */ - object_property_set_int(OBJECT(&s->property), ram_size, "ram-size", &err); ->>>>>>> upstreaming-raspi - if (err) { - error_propagate(errp, err); - return; - } - -<<<<<<< HEAD - memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, - qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); - - /* Property channel */ -======= ->>>>>>> upstreaming-raspi - object_property_set_bool(OBJECT(&s->property), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->mbox_mr, - MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, - qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); - - /* Extended Mass Media Controller */ - object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg", - &err); - if (err) { - error_propagate(errp, err); - return; - } - -<<<<<<< HEAD - object_property_set_bool(OBJECT(&s->sdhci), true, "bcm2835-quirk", &err); - if (err) { - error_propagate(errp, err); - return; - } - -======= ->>>>>>> upstreaming-raspi - object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, -<<<<<<< HEAD - INTERRUPT_VC_ARASANSDIO)); - - /* DMA Channels */ - object_property_set_bool(OBJECT(&s->dma), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); - memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 1, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA1)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 2, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_VC_DMA2)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 3, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_VC_DMA3)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 4, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA4)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 5, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA5)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 6, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA6)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 7, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA7)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 8, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA8)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 9, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA9)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 10, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA10)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 11, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA11)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), 12, - qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA12)); -======= - INTERRUPT_ARASANSDIO)); ->>>>>>> upstreaming-raspi -} - -static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - - dc->realize = bcm2835_peripherals_realize; -} - -static const TypeInfo bcm2835_peripherals_type_info = { - .name = TYPE_BCM2835_PERIPHERALS, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2835PeripheralState), - .instance_init = bcm2835_peripherals_init, - .class_init = bcm2835_peripherals_class_init, -}; - -static void bcm2835_peripherals_register_types(void) -{ - type_register_static(&bcm2835_peripherals_type_info); -} - -type_init(bcm2835_peripherals_register_types) diff --git a/hw/arm/bcm2836.c.orig b/hw/arm/bcm2836.c.orig deleted file mode 100644 index 3f48b9a681..0000000000 --- a/hw/arm/bcm2836.c.orig +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#include "hw/arm/bcm2836.h" -#include "hw/arm/raspi_platform.h" -#include "hw/sysbus.h" -#include "sysemu/sysemu.h" /* for smp_cpus */ -#include "exec/address-spaces.h" - -<<<<<<< HEAD -======= -/* Peripheral base address seen by the CPU */ -#define BCM2836_PERI_BASE 0x3F000000 - -/* "QA7" (Pi2) interrupt controller and mailboxes etc. */ -#define BCM2836_CONTROL_BASE 0x40000000 - ->>>>>>> upstreaming-raspi -static void bcm2836_init(Object *obj) -{ - BCM2836State *s = BCM2836(obj); - int n; - - /* TODO: probably shouldn't be using smp_cpus here */ - assert(smp_cpus <= BCM2836_NCPUS); - for (n = 0; n < smp_cpus; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - "cortex-a15-" TYPE_ARM_CPU); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - - object_initialize(&s->ic, sizeof(s->ic), TYPE_BCM2836_CONTROL); - object_property_add_child(obj, "ic", OBJECT(&s->ic), NULL); - qdev_set_parent_bus(DEVICE(&s->ic), sysbus_get_default()); - - object_initialize(&s->peripherals, sizeof(s->peripherals), - TYPE_BCM2835_PERIPHERALS); - object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals), - &error_abort); -<<<<<<< HEAD - object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), - "vcram-size", &error_abort); -======= ->>>>>>> upstreaming-raspi - qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default()); -} - -static void bcm2836_realize(DeviceState *dev, Error **errp) -{ - BCM2836State *s = BCM2836(dev); -<<<<<<< HEAD -======= - Object *obj; ->>>>>>> upstreaming-raspi - Error *err = NULL; - int n; - - /* common peripherals from bcm2835 */ -<<<<<<< HEAD -======= - obj = object_property_get_link(OBJECT(dev), "ram", &err); - if (obj == NULL) { - error_setg(errp, "%s: required ram link not found: %s", - __func__, error_get_pretty(err)); - return; - } - - object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj, &err); - if (err) { - error_propagate(errp, err); - return; - } - ->>>>>>> upstreaming-raspi - object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, - BCM2836_PERI_BASE, 1); - - /* bcm2836 interrupt controller (and mailboxes, etc.) */ - object_property_set_bool(OBJECT(&s->ic), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ic), 0, BCM2836_CONTROL_BASE); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in_named(DEVICE(&s->ic), "gpu_irq", 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in_named(DEVICE(&s->ic), "gpu_fiq", 0)); - - /* TODO: probably shouldn't be using smp_cpus here */ - assert(smp_cpus <= BCM2836_NCPUS); - for (n = 0; n < smp_cpus; n++) { - /* Mirror bcm2836, which has clusterid set to 0xf */ - s->cpus[n].mp_affinity = 0xF00 | n; - - /* set periphbase/CBAR value for CPU-local registers */ - object_property_set_int(OBJECT(&s->cpus[n]), - BCM2836_PERI_BASE + MCORE_OFFSET, - "reset-cbar", &err); - if (err) { - error_report_err(err); - exit(1); - } - - object_property_set_bool(OBJECT(&s->cpus[n]), true, "realized", &err); - if (err) { - error_report_err(err); - exit(1); - } - - /* Connect irq/fiq outputs from the interrupt controller. */ - qdev_connect_gpio_out_named(DEVICE(&s->ic), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpus[n]), - ARM_CPU_IRQ)); - qdev_connect_gpio_out_named(DEVICE(&s->ic), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpus[n]), - ARM_CPU_FIQ)); - - /* Connect timers from the CPU to the interrupt controller */ - s->cpus[n].gt_timer_outputs[GTIMER_PHYS] - = qdev_get_gpio_in_named(DEVICE(&s->ic), "cntpsirq", 0); - s->cpus[n].gt_timer_outputs[GTIMER_VIRT] - = qdev_get_gpio_in_named(DEVICE(&s->ic), "cntvirq", 0); - } -} - -static void bcm2836_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - - dc->realize = bcm2836_realize; - - /* - * Reason: creates an ARM CPU, thus use after free(), see - * arm_cpu_class_init() - */ - dc->cannot_destroy_with_object_finalize_yet = true; -} - -static const TypeInfo bcm2836_type_info = { - .name = TYPE_BCM2836, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2836State), - .instance_init = bcm2836_init, - .class_init = bcm2836_class_init, -}; - -static void bcm2836_register_types(void) -{ - type_register_static(&bcm2836_type_info); -} - -type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c.orig b/hw/arm/raspi.c.orig deleted file mode 100644 index b69dc34dd4..0000000000 --- a/hw/arm/raspi.c.orig +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -/* Based on versatilepb.c, copyright terms below. */ - -/* - * ARM Versatile Platform/Application Baseboard System emulation. - * - * Copyright (c) 2005-2007 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the GPL. - */ - -<<<<<<< HEAD -#include "hw/arm/bcm2835.h" -======= ->>>>>>> upstreaming-raspi -#include "hw/arm/bcm2836.h" -#include "qemu/error-report.h" -#include "hw/boards.h" -#include "hw/loader.h" -#include "hw/arm/arm.h" -#include "sysemu/sysemu.h" -<<<<<<< HEAD -#include "hw/arm/raspi_platform.h" -======= ->>>>>>> upstreaming-raspi - -#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ -#define MVBAR_ADDR 0x400 /* secure vectors */ -#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ -#define FIRMWARE_ADDR 0x8000 /* Pi loads kernel.img here by default */ - -/* Table of Linux board IDs for different Pi versions */ -static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43}; - -typedef struct RaspiMachineState { - union { - Object obj; -<<<<<<< HEAD - BCM2835State pi1; -======= ->>>>>>> upstreaming-raspi - BCM2836State pi2; - } soc; - MemoryRegion ram; -} RaspiMachineState; - -static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) -{ - static const uint32_t smpboot[] = { - 0xE1A0E00F, /* mov lr, pc */ - 0xE3A0FE42, /* mov pc, #0x420 ;call BOARDSETUP_ADDR */ - 0xEE100FB0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ - 0xE7E10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ - 0xE59F5014, /* ldr r5, =0x400000CC ;load mbox base */ - 0xE320F001, /* 1: yield */ - 0xE7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ - 0xE3530000, /* cmp r3, #0 ;spin while zero */ - 0x0AFFFFFB, /* beq 1b */ - 0xE7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ - 0xE12FFF13, /* bx r3 ;jump to target */ - 0x400000CC, /* (constant: mailbox 3 read/clear base) */ - }; - - assert(SMPBOOT_ADDR + sizeof(smpboot) <= MVBAR_ADDR); - rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start); -} - -static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) -{ - static const uint32_t board_setup[] = { - /* MVBAR_ADDR: secure monitor vectors */ - 0xEAFFFFFE, /* (spin) */ - 0xEAFFFFFE, /* (spin) */ - 0xE1B0F00E, /* movs pc, lr ;SMC exception return */ - 0xEAFFFFFE, /* (spin) */ - 0xEAFFFFFE, /* (spin) */ - 0xEAFFFFFE, /* (spin) */ - 0xEAFFFFFE, /* (spin) */ - 0xEAFFFFFE, /* (spin) */ - /* BOARDSETUP_ADDR */ - 0xE3A00B01, /* mov r0, #0x400 ;MVBAR_ADDR */ - 0xEE0C0F30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ - 0xE3A00031, /* mov r0, #0x31 ;enable AW, FW, NS */ - 0xEE010F11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ - 0xE1A0100E, /* mov r1, lr ;save LR across SMC */ - 0xE1600070, /* smc #0 ;monitor call */ - 0xE1A0F001, /* mov pc, r1 ;return */ - }; - - rom_add_blob_fixed("raspi_boardsetup", board_setup, sizeof(board_setup), - MVBAR_ADDR); -} - -static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) -{ - CPUState *cs = CPU(cpu); - cpu_set_pc(cs, info->smp_loader_start); -} - -static void setup_boot(MachineState *machine, int version, size_t ram_size) -{ - static struct arm_boot_info binfo; - int r; - - binfo.board_id = raspi_boardid[version]; - binfo.ram_size = ram_size; - binfo.nb_cpus = smp_cpus; - binfo.board_setup_addr = BOARDSETUP_ADDR; - binfo.write_board_setup = write_board_setup; - binfo.secure_board_setup = true; - binfo.secure_boot = true; - -<<<<<<< HEAD - /* Pi2 requires SMP setup code */ -======= - /* Pi2 requires SMP setup */ ->>>>>>> upstreaming-raspi - if (version == 2) { - binfo.smp_loader_start = SMPBOOT_ADDR; - binfo.write_secondary_boot = write_smpboot; - binfo.secondary_cpu_reset_hook = reset_secondary; - } - - /* If the user specified a "firmware" image (e.g. UEFI), we bypass - the normal Linux boot process */ - if (machine->firmware) { - /* load the firmware image (typically kernel.img) */ - r = load_image_targphys(machine->firmware, FIRMWARE_ADDR, - ram_size - FIRMWARE_ADDR); - if (r < 0) { - error_report("Failed to load firmware from %s", machine->firmware); - exit(1); - } - - /* set variables so arm_load_kernel does the right thing */ - binfo.entry = FIRMWARE_ADDR; - binfo.firmware_loaded = true; - } else { - /* Just let arm_load_kernel do everything for us... */ - binfo.kernel_filename = machine->kernel_filename; - binfo.kernel_cmdline = machine->kernel_cmdline; - binfo.initrd_filename = machine->initrd_filename; - } - - arm_load_kernel(ARM_CPU(first_cpu), &binfo); -} - -<<<<<<< HEAD -static void raspi_machine_init(MachineState *machine, int version) -{ - RaspiMachineState *s = g_new0(RaspiMachineState, 1); - uint32_t vcram_size; - - /* Initialise the relevant SOC */ - assert(version == 1 || version == 2); - switch (version) { - case 1: - object_initialize(&s->soc.pi1, sizeof(s->soc.pi1), TYPE_BCM2835); - break; - case 2: - object_initialize(&s->soc.pi2, sizeof(s->soc.pi2), TYPE_BCM2836); - break; - } - -======= -static void raspi2_init(MachineState *machine) -{ - RaspiMachineState *s = g_new0(RaspiMachineState, 1); - - /* Initialise the SOC */ - object_initialize(&s->soc.pi2, sizeof(s->soc.pi2), TYPE_BCM2836); ->>>>>>> upstreaming-raspi - object_property_add_child(OBJECT(machine), "soc", &s->soc.obj, - &error_abort); - - /* Allocate and map RAM */ - memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", - machine->ram_size); - memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0); - - /* Setup the SOC */ -<<<<<<< HEAD - object_property_set_bool(&s->soc.obj, true, "realized", &error_abort); - - vcram_size = object_property_get_int(&s->soc.obj, "vcram-size", - &error_abort); - - /* Boot! */ - setup_boot(machine, version, machine->ram_size - vcram_size); -} - -static void raspi1_init(MachineState *machine) -{ - raspi_machine_init(machine, 1); -} - -static void raspi2_init(MachineState *machine) -{ - raspi_machine_init(machine, 2); -} - -static void raspi1_machine_init(MachineClass *mc) -{ - mc->desc = "Raspberry Pi"; - mc->init = raspi1_init; -======= - object_property_add_const_link(&s->soc.obj, "ram", OBJECT(&s->ram), - &error_abort); - object_property_set_bool(&s->soc.obj, true, "realized", &error_abort); - - /* Boot! */ - setup_boot(machine, 2, machine->ram_size); -} - -static void raspi2_machine_init(MachineClass *mc) -{ - mc->desc = "Raspberry Pi 2"; - mc->init = raspi2_init; ->>>>>>> upstreaming-raspi - mc->block_default_type = IF_SD; - mc->no_parallel = 1; - mc->no_floppy = 1; - mc->no_cdrom = 1; -<<<<<<< HEAD - mc->default_ram_size = 512 * 1024 * 1024; -}; -DEFINE_MACHINE("raspi", raspi1_machine_init) - -static void raspi2_machine_init(MachineClass *mc) -{ - raspi1_machine_init(mc); - mc->desc = "Raspberry Pi 2"; - mc->init = raspi2_init; - mc->max_cpus = BCM2836_NCPUS; - mc->default_ram_size = 1024 * 1024 * 1024; -======= - mc->max_cpus = BCM2836_NCPUS; - /* XXX: Temporary restriction in RAM size from the full 1GB. Since - * we do not yet support the framebuffer / GPU, we need to limit - * RAM usable by the OS to sit below the peripherals. */ - mc->default_ram_size = 0x3F000000; /* BCM2836_PERI_BASE */ ->>>>>>> upstreaming-raspi -}; -DEFINE_MACHINE("raspi2", raspi2_machine_init) diff --git a/hw/intc/bcm2835_ic.c.orig b/hw/intc/bcm2835_ic.c.orig deleted file mode 100755 index bc8a370c7f..0000000000 --- a/hw/intc/bcm2835_ic.c.orig +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade -<<<<<<< HEAD -======= - * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann. ->>>>>>> upstreaming-raspi - * This code is licensed under the GNU GPLv2 and later. - * Heavily based on pl190.c, copyright terms below: - * - * Arm PrimeCell PL190 Vector Interrupt Controller - * - * Copyright (c) 2006 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the GPL. - */ - -#include "hw/intc/bcm2835_ic.h" - -#define GPU_IRQS 64 -#define ARM_IRQS 8 - -#define IRQ_PENDING_BASIC 0x00 /* IRQ basic pending */ -#define IRQ_PENDING_1 0x04 /* IRQ pending 1 */ -#define IRQ_PENDING_2 0x08 /* IRQ pending 2 */ -#define FIQ_CONTROL 0x0C /* FIQ register */ -#define IRQ_ENABLE_1 0x10 /* Interrupt enable register 1 */ -#define IRQ_ENABLE_2 0x14 /* Interrupt enable register 2 */ -#define IRQ_ENABLE_BASIC 0x18 /* Base interrupt enable register */ -#define IRQ_DISABLE_1 0x1C /* Interrupt disable register 1 */ -#define IRQ_DISABLE_2 0x20 /* Interrupt disable register 2 */ -#define IRQ_DISABLE_BASIC 0x24 /* Base interrupt disable register */ - -/* Update interrupts. */ -static void bcm2835_ic_update(BCM2835ICState *s) -{ - bool set = false; - - if (s->fiq_enable) { - if (s->fiq_select >= GPU_IRQS) { - /* ARM IRQ */ - set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1); - } else { - set = extract64(s->gpu_irq_level, s->fiq_select, 1); - } - } - qemu_set_irq(s->fiq, set); - - set = (s->gpu_irq_level & s->gpu_irq_enable) - || (s->arm_irq_level & s->arm_irq_enable); - qemu_set_irq(s->irq, set); - -} - -static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level) -{ - BCM2835ICState *s = opaque; -<<<<<<< HEAD -======= - ->>>>>>> upstreaming-raspi - assert(irq >= 0 && irq < 64); - s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0); - bcm2835_ic_update(s); -} - -static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level) -{ - BCM2835ICState *s = opaque; -<<<<<<< HEAD -======= - ->>>>>>> upstreaming-raspi - assert(irq >= 0 && irq < 8); - s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0); - bcm2835_ic_update(s); -} - -static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 }; - -static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size) -{ - BCM2835ICState *s = opaque; - uint32_t res = 0; - uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable; - int i; - - switch (offset) { - case IRQ_PENDING_BASIC: - /* bits 0-7: ARM irqs */ - res = s->arm_irq_level & s->arm_irq_enable; - - /* bits 8 & 9: pending registers 1 & 2 */ - res |= (((uint32_t)gpu_pending) != 0) << 8; - res |= ((gpu_pending >> 32) != 0) << 9; - - /* bits 10-20: selected GPU IRQs */ - for (i = 0; i < ARRAY_SIZE(irq_dups); i++) { - res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10); - } - break; -<<<<<<< HEAD - case IRQ_PENDING_1: /* IRQ pending 1 */ - res = gpu_pending; - break; - case IRQ_PENDING_2: /* IRQ pending 2 */ - res = gpu_pending >> 32; - break; - case FIQ_CONTROL: /* FIQ register */ - res = (s->fiq_enable << 7) | s->fiq_select; - break; - case IRQ_ENABLE_1: /* Interrupt enable register 1 */ - res = s->gpu_irq_enable; - break; - case IRQ_ENABLE_2: /* Interrupt enable register 2 */ - res = s->gpu_irq_enable >> 32; - break; - case IRQ_ENABLE_BASIC: /* Base interrupt enable register */ - res = s->arm_irq_enable; - break; - case IRQ_DISABLE_1: /* Interrupt disable register 1 */ - res = ~s->gpu_irq_enable; - break; - case IRQ_DISABLE_2: /* Interrupt disable register 2 */ - res = ~s->gpu_irq_enable >> 32; - break; - case IRQ_DISABLE_BASIC: /* Base interrupt disable register */ -======= - case IRQ_PENDING_1: - res = gpu_pending; - break; - case IRQ_PENDING_2: - res = gpu_pending >> 32; - break; - case FIQ_CONTROL: - res = (s->fiq_enable << 7) | s->fiq_select; - break; - case IRQ_ENABLE_1: - res = s->gpu_irq_enable; - break; - case IRQ_ENABLE_2: - res = s->gpu_irq_enable >> 32; - break; - case IRQ_ENABLE_BASIC: - res = s->arm_irq_enable; - break; - case IRQ_DISABLE_1: - res = ~s->gpu_irq_enable; - break; - case IRQ_DISABLE_2: - res = ~s->gpu_irq_enable >> 32; - break; - case IRQ_DISABLE_BASIC: ->>>>>>> upstreaming-raspi - res = ~s->arm_irq_enable; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return 0; - } - - return res; -} - -static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val, - unsigned size) -{ - BCM2835ICState *s = opaque; - - switch (offset) { - case FIQ_CONTROL: -<<<<<<< HEAD - s->fiq_select = (val & 0x7f); - s->fiq_enable = (val >> 7) & 0x1; -======= - s->fiq_select = extract32(val, 0, 7); - s->fiq_enable = extract32(val, 7, 1); ->>>>>>> upstreaming-raspi - break; - case IRQ_ENABLE_1: - s->gpu_irq_enable |= val; - break; - case IRQ_ENABLE_2: - s->gpu_irq_enable |= val << 32; - break; - case IRQ_ENABLE_BASIC: - s->arm_irq_enable |= val & 0xff; - break; - case IRQ_DISABLE_1: - s->gpu_irq_enable &= ~val; - break; - case IRQ_DISABLE_2: - s->gpu_irq_enable &= ~(val << 32); - break; - case IRQ_DISABLE_BASIC: - s->arm_irq_enable &= ~val & 0xff; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return; - } - bcm2835_ic_update(s); -} - -static const MemoryRegionOps bcm2835_ic_ops = { - .read = bcm2835_ic_read, - .write = bcm2835_ic_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid.min_access_size = 4, - .valid.max_access_size = 4, -}; - -static void bcm2835_ic_reset(DeviceState *d) -{ - BCM2835ICState *s = BCM2835_IC(d); - - s->gpu_irq_enable = 0; - s->arm_irq_enable = 0; - s->fiq_enable = false; - s->fiq_select = 0; -} - -static void bcm2835_ic_init(Object *obj) -{ - BCM2835ICState *s = BCM2835_IC(obj); - - memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC, - 0x200); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); - - qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq, - BCM2835_IC_GPU_IRQ, GPU_IRQS); - qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq, - BCM2835_IC_ARM_IRQ, ARM_IRQS); - - sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); - sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq); -} - -static const VMStateDescription vmstate_bcm2835_ic = { - .name = TYPE_BCM2835_IC, - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT64(gpu_irq_level, BCM2835ICState), - VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState), - VMSTATE_UINT8(arm_irq_level, BCM2835ICState), - VMSTATE_UINT8(arm_irq_enable, BCM2835ICState), - VMSTATE_BOOL(fiq_enable, BCM2835ICState), - VMSTATE_UINT8(fiq_select, BCM2835ICState), - VMSTATE_END_OF_LIST() - } -}; - -static void bcm2835_ic_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->reset = bcm2835_ic_reset; - dc->vmsd = &vmstate_bcm2835_ic; -} - -static TypeInfo bcm2835_ic_info = { - .name = TYPE_BCM2835_IC, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2835ICState), - .class_init = bcm2835_ic_class_init, - .instance_init = bcm2835_ic_init, -}; - -static void bcm2835_ic_register_types(void) -{ - type_register_static(&bcm2835_ic_info); -} - -type_init(bcm2835_ic_register_types) diff --git a/hw/intc/bcm2836_control.c.orig b/hw/intc/bcm2836_control.c.orig deleted file mode 100755 index 2628ed7056..0000000000 --- a/hw/intc/bcm2836_control.c.orig +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Rasperry Pi 2 emulation ARM control logic module. - * Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * -<<<<<<< HEAD -======= - * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - * ->>>>>>> upstreaming-raspi - * At present, only implements interrupt routing, and mailboxes (i.e., - * not local timer, PMU interrupt, or AXI counters). - * - * Ref: - * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf -<<<<<<< HEAD - * - * Based on bcm2835_ic.c, terms below... - */ - -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -/* Heavily based on pl190.c, copyright terms below. */ - -/* - * Arm PrimeCell PL190 Vector Interrupt Controller - * - * Copyright (c) 2006 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the GPL. -======= ->>>>>>> upstreaming-raspi - */ - -#include "hw/intc/bcm2836_control.h" - -#define ROUTE_CORE(x) ((x) & 0x3) -#define ROUTE_FIQ(x) (((x) & 0x4) != 0) - -#define IRQ_BIT(cntrl, num) (((cntrl) & (1 << (num))) != 0) -#define FIQ_BIT(cntrl, num) (((cntrl) & (1 << ((num) + 4))) != 0) - -#define IRQ_CNTPSIRQ 0 -#define IRQ_CNTPNSIRQ 1 -#define IRQ_CNTHPIRQ 2 -#define IRQ_CNTVIRQ 3 -#define IRQ_MAILBOX0 4 -#define IRQ_MAILBOX1 5 -#define IRQ_MAILBOX2 6 -#define IRQ_MAILBOX3 7 -#define IRQ_GPU 8 -#define IRQ_PMU 9 -#define IRQ_AXI 10 -#define IRQ_TIMER 11 -#define IRQ_MAX IRQ_TIMER - -/* Update interrupts. */ -static void bcm2836_control_update(BCM2836ControlState *s) -{ - int i, j; - -<<<<<<< HEAD - /* - * reset pending IRQs/FIQs - */ - -======= - /* reset pending IRQs/FIQs */ ->>>>>>> upstreaming-raspi - for (i = 0; i < BCM2836_NCORES; i++) { - s->irqsrc[i] = s->fiqsrc[i] = 0; - } - -<<<<<<< HEAD - /* - * apply routing logic, update status regs - */ - -======= - /* apply routing logic, update status regs */ ->>>>>>> upstreaming-raspi - if (s->gpu_irq) { - assert(s->route_gpu_irq < BCM2836_NCORES); - s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU; - } - - if (s->gpu_fiq) { - assert(s->route_gpu_fiq < BCM2836_NCORES); - s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU; - } - - for (i = 0; i < BCM2836_NCORES; i++) { - /* handle local interrupts for this core */ - if (s->localirqs[i]) { -<<<<<<< HEAD -======= - /* sanity check localirqs: mailboxes are handled below */ ->>>>>>> upstreaming-raspi - assert(s->localirqs[i] < (1 << IRQ_MAILBOX0)); - for (j = 0; j < IRQ_MAILBOX0; j++) { - if ((s->localirqs[i] & (1 << j)) != 0) { - /* local interrupt j is set */ - if (FIQ_BIT(s->timercontrol[i], j)) { - /* deliver a FIQ */ - s->fiqsrc[i] |= (uint32_t)1 << j; - } else if (IRQ_BIT(s->timercontrol[i], j)) { - /* deliver an IRQ */ - s->irqsrc[i] |= (uint32_t)1 << j; - } else { - /* the interrupt is masked */ - } - } - } - } - - /* handle mailboxes for this core */ - for (j = 0; j < BCM2836_MBPERCORE; j++) { - if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) { - /* mailbox j is set */ - if (FIQ_BIT(s->mailboxcontrol[i], j)) { - /* deliver a FIQ */ - s->fiqsrc[i] |= (uint32_t)1 << (j + IRQ_MAILBOX0); - } else if (IRQ_BIT(s->mailboxcontrol[i], j)) { - /* deliver an IRQ */ - s->irqsrc[i] |= (uint32_t)1 << (j + IRQ_MAILBOX0); - } else { - /* the interrupt is masked */ - } - } - } - } - -<<<<<<< HEAD - /* - * call set_irq appropriately for each output - */ - -======= - /* call set_irq appropriately for each output */ ->>>>>>> upstreaming-raspi - for (i = 0; i < BCM2836_NCORES; i++) { - qemu_set_irq(s->irq[i], s->irqsrc[i] != 0); - qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0); - } -} - -static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq, - int level) -{ - BCM2836ControlState *s = opaque; - - assert(core >= 0 && core < BCM2836_NCORES); - assert(local_irq >= 0 && local_irq <= IRQ_CNTVIRQ); - - if (level) { - s->localirqs[core] |= 1 << local_irq; - } else { - s->localirqs[core] &= ~((uint32_t)1 << local_irq); - } - - bcm2836_control_update(s); -} - -/* XXX: the following wrapper functions are a kludgy workaround, - * needed because I can't seem to pass useful information in the "irq" - * parameter when using named interrupts. Feel free to clean this up! - */ - -static void bcm2836_control_set_local_irq0(void *opaque, int core, int level) -{ - bcm2836_control_set_local_irq(opaque, core, 0, level); -} - -static void bcm2836_control_set_local_irq1(void *opaque, int core, int level) -{ - bcm2836_control_set_local_irq(opaque, core, 1, level); -} - -static void bcm2836_control_set_local_irq2(void *opaque, int core, int level) -{ - bcm2836_control_set_local_irq(opaque, core, 2, level); -} - -static void bcm2836_control_set_local_irq3(void *opaque, int core, int level) -{ - bcm2836_control_set_local_irq(opaque, core, 3, level); -} - -static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level) -{ - BCM2836ControlState *s = opaque; - - s->gpu_irq = level; - - bcm2836_control_update(s); -} - -static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level) -{ - BCM2836ControlState *s = opaque; - - s->gpu_fiq = level; - - bcm2836_control_update(s); -} - -static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size) -{ - BCM2836ControlState *s = opaque; - - if (offset == 0xc) { - /* GPU interrupt routing */ - assert(s->route_gpu_fiq < BCM2836_NCORES - && s->route_gpu_irq < BCM2836_NCORES); - return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq; - } else if (offset >= 0x40 && offset < 0x50) { - /* Timer interrupt control registers */ - return s->timercontrol[(offset - 0x40) >> 2]; - } else if (offset >= 0x50 && offset < 0x60) { - /* Mailbox interrupt control registers */ - return s->mailboxcontrol[(offset - 0x50) >> 2]; - } else if (offset >= 0x60 && offset < 0x70) { - /* IRQ source registers */ - return s->irqsrc[(offset - 0x60) >> 2]; - } else if (offset >= 0x70 && offset < 0x80) { - /* FIQ source registers */ - return s->fiqsrc[(offset - 0x70) >> 2]; - } else if (offset >= 0xc0 && offset < 0x100) { - /* Mailboxes */ - return s->mailboxes[(offset - 0xc0) >> 2]; - } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return 0; - } -} - -static void bcm2836_control_write(void *opaque, hwaddr offset, - uint64_t val, unsigned size) -{ - BCM2836ControlState *s = opaque; - - if (offset == 0xc) { - /* GPU interrupt routing */ - s->route_gpu_irq = val & 0x3; - s->route_gpu_fiq = (val >> 2) & 0x3; - } else if (offset >= 0x40 && offset < 0x50) { - /* Timer interrupt control registers */ - s->timercontrol[(offset - 0x40) >> 2] = val & 0xff; - } else if (offset >= 0x50 && offset < 0x60) { - /* Mailbox interrupt control registers */ - s->mailboxcontrol[(offset - 0x50) >> 2] = val & 0xff; - } else if (offset >= 0x80 && offset < 0xc0) { - /* Mailbox set registers */ - s->mailboxes[(offset - 0x80) >> 2] |= val; - } else if (offset >= 0xc0 && offset < 0x100) { - /* Mailbox clear registers */ - s->mailboxes[(offset - 0xc0) >> 2] &= ~val; - } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return; - } - - bcm2836_control_update(s); -} - -static const MemoryRegionOps bcm2836_control_ops = { - .read = bcm2836_control_read, - .write = bcm2836_control_write, - .endianness = DEVICE_NATIVE_ENDIAN, -<<<<<<< HEAD -======= - .valid.min_access_size = 4, - .valid.max_access_size = 4, ->>>>>>> upstreaming-raspi -}; - -static void bcm2836_control_reset(DeviceState *d) -{ - BCM2836ControlState *s = BCM2836_CONTROL(d); - int i; - - s->route_gpu_irq = s->route_gpu_fiq = 0; - - for (i = 0; i < BCM2836_NCORES; i++) { - s->timercontrol[i] = 0; - s->mailboxcontrol[i] = 0; - } - - for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) { - s->mailboxes[i] = 0; - } -} - -static void bcm2836_control_init(Object *obj) -{ - BCM2836ControlState *s = BCM2836_CONTROL(obj); - DeviceState *dev = DEVICE(obj); - - memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s, - TYPE_BCM2836_CONTROL, 0x100); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); - - /* inputs from each CPU core */ - qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq0, "cntpsirq", - BCM2836_NCORES); - qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq1, "cntpnsirq", - BCM2836_NCORES); - qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq2, "cnthpirq", - BCM2836_NCORES); - qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq3, "cntvirq", - BCM2836_NCORES); - /* qdev_init_gpio_in_named(dev, bcm2836_control_set_pmu_irq, "pmuirq", - BCM2836_NCORES); */ - - /* IRQ and FIQ inputs from upstream bcm2835 controller */ - qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu_irq", 1); - qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu_fiq", 1); - - /* outputs to CPU cores */ - qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES); - qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES); -} - -static const VMStateDescription vmstate_bcm2836_control = { - .name = TYPE_BCM2836_CONTROL, - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState, - BCM2836_NCORES * BCM2836_MBPERCORE), - VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState), - VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState), - VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES), - VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState, - BCM2836_NCORES), - VMSTATE_END_OF_LIST() - } -}; - -static void bcm2836_control_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->reset = bcm2836_control_reset; - dc->vmsd = &vmstate_bcm2836_control; -} - -static TypeInfo bcm2836_control_info = { - .name = TYPE_BCM2836_CONTROL, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2836ControlState), - .class_init = bcm2836_control_class_init, - .instance_init = bcm2836_control_init, -}; - -static void bcm2836_control_register_types(void) -{ - type_register_static(&bcm2836_control_info); -} - -type_init(bcm2836_control_register_types) diff --git a/hw/misc/Makefile.objs.orig b/hw/misc/Makefile.objs.orig deleted file mode 100755 index 96ed107b8b..0000000000 --- a/hw/misc/Makefile.objs.orig +++ /dev/null @@ -1,53 +0,0 @@ -common-obj-$(CONFIG_APPLESMC) += applesmc.o -common-obj-$(CONFIG_MAX111X) += max111x.o -common-obj-$(CONFIG_TMP105) += tmp105.o -common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o -common-obj-$(CONFIG_SGA) += sga.o -common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o -common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o - -obj-$(CONFIG_VMPORT) += vmport.o - -# ARM devices -common-obj-$(CONFIG_PL310) += arm_l2x0.o -common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o -common-obj-$(CONFIG_A9SCU) += a9scu.o -common-obj-$(CONFIG_ARM11SCU) += arm11scu.o - -# PKUnity SoC devices -common-obj-$(CONFIG_PUV3) += puv3_pm.o - -common-obj-$(CONFIG_MACIO) += macio/ - -obj-$(CONFIG_IVSHMEM) += ivshmem.o - -obj-$(CONFIG_REALVIEW) += arm_sysctl.o -obj-$(CONFIG_NSERIES) += cbus.o -obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o -obj-$(CONFIG_IMX) += imx_ccm.o -obj-$(CONFIG_IMX) += imx31_ccm.o -obj-$(CONFIG_IMX) += imx25_ccm.o -obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o -obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o -obj-$(CONFIG_MAINSTONE) += mst_fpga.o -obj-$(CONFIG_OMAP) += omap_clk.o -obj-$(CONFIG_OMAP) += omap_gpmc.o -obj-$(CONFIG_OMAP) += omap_l4.o -obj-$(CONFIG_OMAP) += omap_sdrc.o -obj-$(CONFIG_OMAP) += omap_tap.o -obj-$(CONFIG_RASPI) += bcm2835_mbox.o -<<<<<<< HEAD -obj-$(CONFIG_RASPI) += bcm2835_mphi.o -obj-$(CONFIG_RASPI) += bcm2835_power.o -======= ->>>>>>> upstreaming-raspi -obj-$(CONFIG_RASPI) += bcm2835_property.o -obj-$(CONFIG_SLAVIO) += slavio_misc.o -obj-$(CONFIG_ZYNQ) += zynq_slcr.o -obj-$(CONFIG_ZYNQ) += zynq-xadc.o -obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o - -obj-$(CONFIG_PVPANIC) += pvpanic.o -obj-$(CONFIG_EDU) += edu.o -obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o diff --git a/hw/misc/bcm2835_mbox.c.orig b/hw/misc/bcm2835_mbox.c.orig deleted file mode 100644 index cb9a866bf2..0000000000 --- a/hw/misc/bcm2835_mbox.c.orig +++ /dev/null @@ -1,406 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - * - * This file models the system mailboxes, which are used for - * communication with low-bandwidth GPU peripherals. Refs: - * https://github.com/raspberrypi/firmware/wiki/Mailboxes - * https://github.com/raspberrypi/firmware/wiki/Accessing-mailboxes - */ - -#include "hw/misc/bcm2835_mbox.h" - -<<<<<<< HEAD -/* Mailbox status register (...0x98) */ -======= -#define MAIL0_PEEK 0x90 -#define MAIL0_SENDER 0x94 -#define MAIL1_STATUS 0xb8 - -/* Mailbox status register */ -#define MAIL0_STATUS 0x98 ->>>>>>> upstreaming-raspi -#define ARM_MS_FULL 0x80000000 -#define ARM_MS_EMPTY 0x40000000 -#define ARM_MS_LEVEL 0x400000FF /* Max. value depends on mailbox depth */ - -<<<<<<< HEAD -/* MAILBOX config/status register (...0x9C) */ -======= -/* MAILBOX config/status register */ -#define MAIL0_CONFIG 0x9c ->>>>>>> upstreaming-raspi -/* ANY write to this register clears the error bits! */ -#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mbox irq enable: has data */ -#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mbox irq enable: has space */ -#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mbox irq enable: Opp is empty */ -#define ARM_MC_MAIL_CLEAR 0x00000008 /* mbox clear write 1, then 0 */ -#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mbox irq pending: has space */ -#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mbox irq pending: Opp is empty */ -#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mbox irq pending */ -/* Bit 7 is unused */ -#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ - -static void mbox_update_status(BCM2835Mbox *mb) -{ - mb->status &= ~(ARM_MS_EMPTY | ARM_MS_FULL); - if (mb->count == 0) { - mb->status |= ARM_MS_EMPTY; - } else if (mb->count == MBOX_SIZE) { - mb->status |= ARM_MS_FULL; - } -} - -<<<<<<< HEAD -static void mbox_init(BCM2835Mbox *mb) -======= -static void mbox_reset(BCM2835Mbox *mb) ->>>>>>> upstreaming-raspi -{ - int n; - - mb->count = 0; - mb->config = 0; - for (n = 0; n < MBOX_SIZE; n++) { - mb->reg[n] = MBOX_INVALID_DATA; - } - mbox_update_status(mb); -} - -static uint32_t mbox_pull(BCM2835Mbox *mb, int index) -{ - int n; - uint32_t val; - - assert(mb->count > 0); - assert(index < mb->count); - - val = mb->reg[index]; - for (n = index + 1; n < mb->count; n++) { - mb->reg[n - 1] = mb->reg[n]; - } - mb->count--; - mb->reg[mb->count] = MBOX_INVALID_DATA; - - mbox_update_status(mb); - - return val; -} - -static void mbox_push(BCM2835Mbox *mb, uint32_t val) -{ - assert(mb->count < MBOX_SIZE); - mb->reg[mb->count++] = val; - mbox_update_status(mb); -} - -static void bcm2835_mbox_update(BCM2835MboxState *s) -{ - uint32_t value; - bool set; - int n; - -<<<<<<< HEAD - /* Avoid unwanted recursive calls */ -======= ->>>>>>> upstreaming-raspi - s->mbox_irq_disabled = true; - - /* Get pending responses and put them in the vc->arm mbox, - * as long as it's not full */ - for (n = 0; n < MBOX_CHAN_COUNT; n++) { - while (s->available[n] && !(s->mbox[0].status & ARM_MS_FULL)) { - value = ldl_phys(&s->mbox_as, n << MBOX_AS_CHAN_SHIFT); -<<<<<<< HEAD - if (value == MBOX_INVALID_DATA) { - /* Interrupt pending, but there's no data. Hmmm... */ - hw_error("%s: spurious interrupt on channel %d", __func__, n); - } -======= - assert(value != MBOX_INVALID_DATA); /* Pending interrupt but no data */ ->>>>>>> upstreaming-raspi - mbox_push(&s->mbox[0], value); - } - } - - /* Try to push pending requests from the arm->vc mbox */ - /* TODO (?) */ - - /* Re-enable calls from the IRQ routine */ - s->mbox_irq_disabled = false; - - /* Update ARM IRQ status */ - set = false; - s->mbox[0].config &= ~ARM_MC_IHAVEDATAIRQPEND; - if (!(s->mbox[0].status & ARM_MS_EMPTY)) { - s->mbox[0].config |= ARM_MC_IHAVEDATAIRQPEND; - if (s->mbox[0].config & ARM_MC_IHAVEDATAIRQEN) { - set = true; - } - } - qemu_set_irq(s->arm_irq, set); -} - -static void bcm2835_mbox_set_irq(void *opaque, int irq, int level) -{ - BCM2835MboxState *s = opaque; - - s->available[irq] = level; - - /* avoid recursively calling bcm2835_mbox_update when the interrupt -<<<<<<< HEAD - * status changes due to the ldl_phys call within that function */ -======= - * status changes due to the ldl_phys call within that function - */ ->>>>>>> upstreaming-raspi - if (!s->mbox_irq_disabled) { - bcm2835_mbox_update(s); - } -} - -static uint64_t bcm2835_mbox_read(void *opaque, hwaddr offset, unsigned size) -{ - BCM2835MboxState *s = opaque; - uint32_t res = 0; - - offset &= 0xff; - - switch (offset) { -<<<<<<< HEAD - case 0x80 ... 0x8c: /* MAIL0_READ */ -======= - case 0x80 ... 0x8c: /* MAIL0_READ */ ->>>>>>> upstreaming-raspi - if (s->mbox[0].status & ARM_MS_EMPTY) { - res = MBOX_INVALID_DATA; - } else { - res = mbox_pull(&s->mbox[0], 0); - } - break; -<<<<<<< HEAD - case 0x90: /* MAIL0_PEEK */ - res = s->mbox[0].reg[0]; - break; - case 0x94: /* MAIL0_SENDER */ - break; - case 0x98: /* MAIL0_STATUS */ - res = s->mbox[0].status; - break; - case 0x9c: /* MAIL0_CONFIG */ - res = s->mbox[0].config; - break; - case 0xb8: /* MAIL1_STATUS */ - res = s->mbox[1].status; - break; -======= - - case MAIL0_PEEK: - res = s->mbox[0].reg[0]; - break; - - case MAIL0_SENDER: - break; - - case MAIL0_STATUS: - res = s->mbox[0].status; - break; - - case MAIL0_CONFIG: - res = s->mbox[0].config; - break; - - case MAIL1_STATUS: - res = s->mbox[1].status; - break; - ->>>>>>> upstreaming-raspi - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return 0; - } - - bcm2835_mbox_update(s); - - return res; -} - -static void bcm2835_mbox_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - BCM2835MboxState *s = opaque; - hwaddr childaddr; - uint8_t ch; - - offset &= 0xff; - - switch (offset) { -<<<<<<< HEAD - case 0x94: /* MAIL0_SENDER */ - break; - - case 0x9c: /* MAIL0_CONFIG */ -======= - case MAIL0_SENDER: - break; - - case MAIL0_CONFIG: ->>>>>>> upstreaming-raspi - s->mbox[0].config &= ~ARM_MC_IHAVEDATAIRQEN; - s->mbox[0].config |= value & ARM_MC_IHAVEDATAIRQEN; - break; - -<<<<<<< HEAD - case 0xa0 ... 0xac: -======= - case 0xa0 ... 0xac: /* MAIL1_WRITE */ ->>>>>>> upstreaming-raspi - if (s->mbox[1].status & ARM_MS_FULL) { - /* Mailbox full */ - qemu_log_mask(LOG_GUEST_ERROR, "%s: mailbox full\n", __func__); - } else { - ch = value & 0xf; - if (ch < MBOX_CHAN_COUNT) { - childaddr = ch << MBOX_AS_CHAN_SHIFT; - if (ldl_phys(&s->mbox_as, childaddr + MBOX_AS_PENDING)) { - /* Child busy, push delayed. Push it in the arm->vc mbox */ - mbox_push(&s->mbox[1], value); - } else { - /* Push it directly to the child device */ - stl_phys(&s->mbox_as, childaddr, value); - } - } else { - /* Invalid channel number */ - qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid channel %u\n", - __func__, ch); - } - } - break; - - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return; - } - - bcm2835_mbox_update(s); -} - -static const MemoryRegionOps bcm2835_mbox_ops = { - .read = bcm2835_mbox_read, - .write = bcm2835_mbox_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid.min_access_size = 4, - .valid.max_access_size = 4, -}; - -/* vmstate of a single mailbox */ -static const VMStateDescription vmstate_bcm2835_mbox_box = { - .name = TYPE_BCM2835_MBOX "_box", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(reg, BCM2835Mbox, MBOX_SIZE), - VMSTATE_UINT32(count, BCM2835Mbox), - VMSTATE_UINT32(status, BCM2835Mbox), - VMSTATE_UINT32(config, BCM2835Mbox), - VMSTATE_END_OF_LIST() - } -}; - -/* vmstate of the entire device */ -static const VMStateDescription vmstate_bcm2835_mbox = { - .name = TYPE_BCM2835_MBOX, - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, - .fields = (VMStateField[]) { - VMSTATE_BOOL_ARRAY(available, BCM2835MboxState, MBOX_CHAN_COUNT), - VMSTATE_STRUCT_ARRAY(mbox, BCM2835MboxState, 2, 1, - vmstate_bcm2835_mbox_box, BCM2835Mbox), - VMSTATE_END_OF_LIST() - } -}; - -static void bcm2835_mbox_init(Object *obj) -{ - BCM2835MboxState *s = BCM2835_MBOX(obj); -<<<<<<< HEAD -======= - ->>>>>>> upstreaming-raspi - memory_region_init_io(&s->iomem, obj, &bcm2835_mbox_ops, s, - TYPE_BCM2835_MBOX, 0x400); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); - sysbus_init_irq(SYS_BUS_DEVICE(s), &s->arm_irq); - qdev_init_gpio_in(DEVICE(s), bcm2835_mbox_set_irq, MBOX_CHAN_COUNT); -} - -static void bcm2835_mbox_reset(DeviceState *dev) -{ - BCM2835MboxState *s = BCM2835_MBOX(dev); - int n; - -<<<<<<< HEAD - mbox_init(&s->mbox[0]); - mbox_init(&s->mbox[1]); -======= - mbox_reset(&s->mbox[0]); - mbox_reset(&s->mbox[1]); ->>>>>>> upstreaming-raspi - s->mbox_irq_disabled = false; - for (n = 0; n < MBOX_CHAN_COUNT; n++) { - s->available[n] = false; - } -} - -static void bcm2835_mbox_realize(DeviceState *dev, Error **errp) -{ - BCM2835MboxState *s = BCM2835_MBOX(dev); - Object *obj; - Error *err = NULL; - -<<<<<<< HEAD - obj = object_property_get_link(OBJECT(dev), "mbox_mr", &err); - if (obj == NULL) { - error_setg(errp, "%s: required mbox_mr link not found: %s", -======= - obj = object_property_get_link(OBJECT(dev), "mbox-mr", &err); - if (obj == NULL) { - error_setg(errp, "%s: required mbox-mr link not found: %s", ->>>>>>> upstreaming-raspi - __func__, error_get_pretty(err)); - return; - } - - s->mbox_mr = MEMORY_REGION(obj); - address_space_init(&s->mbox_as, s->mbox_mr, NULL); - bcm2835_mbox_reset(dev); -} - -static void bcm2835_mbox_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = bcm2835_mbox_realize; - dc->reset = bcm2835_mbox_reset; - dc->vmsd = &vmstate_bcm2835_mbox; -} - -static TypeInfo bcm2835_mbox_info = { - .name = TYPE_BCM2835_MBOX, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2835MboxState), - .class_init = bcm2835_mbox_class_init, - .instance_init = bcm2835_mbox_init, -}; - -static void bcm2835_mbox_register_types(void) -{ - type_register_static(&bcm2835_mbox_info); -} - -type_init(bcm2835_mbox_register_types) diff --git a/hw/misc/bcm2835_property.c.orig b/hw/misc/bcm2835_property.c.orig deleted file mode 100755 index 68a4da21f4..0000000000 --- a/hw/misc/bcm2835_property.c.orig +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -#include "hw/misc/bcm2835_property.h" -#include "hw/misc/bcm2835_mbox_defs.h" - -/* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */ - -static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) -{ - uint32_t tag; - uint32_t bufsize; - uint32_t tot_len; -<<<<<<< HEAD - int n; - size_t resplen; - uint32_t offset, length, color; - uint32_t tmp; - uint32_t xres, yres, xoffset, yoffset, bpp, pixo, alpha; - uint32_t *newxres = NULL, *newyres = NULL, *newxoffset = NULL, - *newyoffset = NULL, *newbpp = NULL, *newpixo = NULL, *newalpha = NULL; -======= - size_t resplen; - uint32_t tmp; ->>>>>>> upstreaming-raspi - - value &= ~0xf; - - s->addr = value; - - tot_len = ldl_phys(&s->dma_as, value); - - /* @(addr + 4) : Buffer response code */ - value = s->addr + 8; - while (value + 8 <= s->addr + tot_len) { - tag = ldl_phys(&s->dma_as, value); - bufsize = ldl_phys(&s->dma_as, value + 4); - /* @(value + 8) : Request/response indicator */ - resplen = 0; - switch (tag) { - case 0x00000000: /* End tag */ - break; - case 0x00000001: /* Get firmware revision */ - stl_phys(&s->dma_as, value + 12, 346337); - resplen = 4; - break; - - case 0x00010001: /* Get board model */ - resplen = 4; - break; - case 0x00010002: /* Get board revision */ - resplen = 4; - break; - case 0x00010003: /* Get board MAC address */ - /* write the first four bytes of the 6-byte MAC */ - stl_phys(&s->dma_as, value + 12, 0xB827EBD0); - /* write the last two bytes, avoid any write past the buffer end */ - stb_phys(&s->dma_as, value + 16, 0xEE); - stb_phys(&s->dma_as, value + 17, 0xDF); - resplen = 6; - break; - case 0x00010004: /* Get board serial */ - resplen = 8; - break; - case 0x00010005: /* Get ARM memory */ - /* base */ - stl_phys(&s->dma_as, value + 12, 0); - /* size */ -<<<<<<< HEAD - stl_phys(&s->dma_as, value + 16, s->fbdev->vcram_base); - resplen = 8; - break; - case 0x00010006: /* Get VC memory */ - /* base */ - stl_phys(&s->dma_as, value + 12, s->fbdev->vcram_base); - /* size */ - stl_phys(&s->dma_as, value + 16, s->fbdev->vcram_size); -======= - stl_phys(&s->dma_as, value + 16, s->ram_size); ->>>>>>> upstreaming-raspi - resplen = 8; - break; - case 0x00028001: /* Set power state */ - /* Assume that whatever device they asked for exists, - * and we'll just claim we set it to the desired state */ - tmp = ldl_phys(&s->dma_as, value + 16); - stl_phys(&s->dma_as, value + 16, (tmp & 1)); - resplen = 8; - break; - - /* Clocks */ - - case 0x00030001: /* Get clock state */ - stl_phys(&s->dma_as, value + 16, 0x1); - resplen = 8; - break; - - case 0x00038001: /* Set clock state */ - resplen = 8; - break; - - case 0x00030002: /* Get clock rate */ - case 0x00030004: /* Get max clock rate */ - case 0x00030007: /* Get min clock rate */ - switch (ldl_phys(&s->dma_as, value + 12)) { - case 1: /* EMMC */ - stl_phys(&s->dma_as, value + 16, 50000000); - break; - case 2: /* UART */ - stl_phys(&s->dma_as, value + 16, 3000000); - break; - default: - stl_phys(&s->dma_as, value + 16, 700000000); - break; - } - resplen = 8; - break; - - case 0x00038002: /* Set clock rate */ - case 0x00038004: /* Set max clock rate */ - case 0x00038007: /* Set min clock rate */ - resplen = 8; - break; - - /* Temperature */ - - case 0x00030006: /* Get temperature */ - stl_phys(&s->dma_as, value + 16, 25000); - resplen = 8; - break; - - case 0x0003000A: /* Get max temperature */ - stl_phys(&s->dma_as, value + 16, 99000); - resplen = 8; - break; - - -<<<<<<< HEAD - /* Frame buffer */ - - case 0x00040001: /* Allocate buffer */ - stl_phys(&s->dma_as, value + 12, s->fbdev->base); - stl_phys(&s->dma_as, value + 16, s->fbdev->size); - resplen = 8; - break; - case 0x00048001: /* Release buffer */ - resplen = 0; - break; - case 0x00040002: /* Blank screen */ - resplen = 4; - break; - case 0x00040003: /* Get display width/height */ - case 0x00040004: - stl_phys(&s->dma_as, value + 12, s->fbdev->xres); - stl_phys(&s->dma_as, value + 16, s->fbdev->yres); - resplen = 8; - break; - case 0x00044003: /* Test display width/height */ - case 0x00044004: - resplen = 8; - break; - case 0x00048003: /* Set display width/height */ - case 0x00048004: - xres = ldl_phys(&s->dma_as, value + 12); - newxres = &xres; - yres = ldl_phys(&s->dma_as, value + 16); - newyres = &yres; - resplen = 8; - break; - case 0x00040005: /* Get depth */ - stl_phys(&s->dma_as, value + 12, s->fbdev->bpp); - resplen = 4; - break; - case 0x00044005: /* Test depth */ - resplen = 4; - break; - case 0x00048005: /* Set depth */ - bpp = ldl_phys(&s->dma_as, value + 12); - newbpp = &bpp; - resplen = 4; - break; - case 0x00040006: /* Get pixel order */ - stl_phys(&s->dma_as, value + 12, s->fbdev->pixo); - resplen = 4; - break; - case 0x00044006: /* Test pixel order */ - resplen = 4; - break; - case 0x00048006: /* Set pixel order */ - pixo = ldl_phys(&s->dma_as, value + 12); - newpixo = &pixo; - resplen = 4; - break; - case 0x00040007: /* Get alpha */ - stl_phys(&s->dma_as, value + 12, s->fbdev->alpha); - resplen = 4; - break; - case 0x00044007: /* Test pixel alpha */ - resplen = 4; - break; - case 0x00048007: /* Set alpha */ - alpha = ldl_phys(&s->dma_as, value + 12); - newalpha = α - resplen = 4; - break; - case 0x00040008: /* Get pitch */ - stl_phys(&s->dma_as, value + 12, s->fbdev->pitch); - resplen = 4; - break; - case 0x00040009: /* Get virtual offset */ - stl_phys(&s->dma_as, value + 12, s->fbdev->xoffset); - stl_phys(&s->dma_as, value + 16, s->fbdev->yoffset); - resplen = 8; - break; - case 0x00044009: /* Test virtual offset */ - resplen = 8; - break; - case 0x00048009: /* Set virtual offset */ - xoffset = ldl_phys(&s->dma_as, value + 12); - newxoffset = &xoffset; - yoffset = ldl_phys(&s->dma_as, value + 16); - newyoffset = &yoffset; - /* - stl_phys(&s->dma_as, value + 12, bcm2835_fb.xres); - stl_phys(&s->dma_as, value + 16, bcm2835_fb.yres); - */ - resplen = 8; - break; - case 0x0004000a: /* Get/Test/Set overscan */ - case 0x0004400a: - case 0x0004800a: - stl_phys(&s->dma_as, value + 12, 0); - stl_phys(&s->dma_as, value + 16, 0); - stl_phys(&s->dma_as, value + 20, 0); - stl_phys(&s->dma_as, value + 24, 0); - resplen = 16; - break; - - case 0x0004800b: /* Set palette */ - offset = ldl_phys(&s->dma_as, value + 12); - length = ldl_phys(&s->dma_as, value + 16); - n = 0; - while (n < length - offset) { - color = ldl_phys(&s->dma_as, value + 20 + (n << 2)); - stl_phys(&s->dma_as, - s->fbdev->vcram_base + ((offset + n) << 2), color); - n++; - } - stl_phys(&s->dma_as, value + 12, 0); - resplen = 4; - break; - -======= ->>>>>>> upstreaming-raspi - case 0x00060001: /* Get DMA channels */ - /* channels 2-5 */ - stl_phys(&s->dma_as, value + 12, 0x003C); - resplen = 4; - break; - - case 0x00050001: /* Get command line */ - resplen = 0; - break; - - default: - qemu_log_mask(LOG_GUEST_ERROR, - "bcm2835_property: unhandled tag %08x\n", tag); - break; - } - - if (tag == 0) { - break; - } - - stl_phys(&s->dma_as, value + 8, (1 << 31) | resplen); - value += bufsize + 12; - } - -<<<<<<< HEAD - if (newxres || newyres || newxoffset || newyoffset || newbpp || newpixo - || newalpha) { - bcm2835_fb_reconfigure(s->fbdev, newxres, newyres, newxoffset, - newyoffset, newbpp, newpixo, newalpha); - } - -======= ->>>>>>> upstreaming-raspi - /* Buffer response code */ - stl_phys(&s->dma_as, s->addr + 4, (1 << 31)); -} - -static uint64_t bcm2835_property_read(void *opaque, hwaddr offset, - unsigned size) -{ - BCM2835PropertyState *s = opaque; - uint32_t res = 0; - - switch (offset) { - case MBOX_AS_DATA: - res = MBOX_CHAN_PROPERTY | s->addr; - s->pending = false; - qemu_set_irq(s->mbox_irq, 0); - break; - - case MBOX_AS_PENDING: - res = s->pending; - break; - - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return 0; - } - - return res; -} - -static void bcm2835_property_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - BCM2835PropertyState *s = opaque; - - switch (offset) { - case MBOX_AS_DATA: - if (!s->pending) { - s->pending = true; - bcm2835_property_mbox_push(s, value); - qemu_set_irq(s->mbox_irq, 1); - } - break; - - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", - __func__, offset); - return; - } - -} - -static const MemoryRegionOps bcm2835_property_ops = { - .read = bcm2835_property_read, - .write = bcm2835_property_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid.min_access_size = 4, - .valid.max_access_size = 4, -}; - -static const VMStateDescription vmstate_bcm2835_property = { - .name = TYPE_BCM2835_PROPERTY, - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(addr, BCM2835PropertyState), - VMSTATE_BOOL(pending, BCM2835PropertyState), - VMSTATE_END_OF_LIST() - } -}; - -static void bcm2835_property_init(Object *obj) -{ - BCM2835PropertyState *s = BCM2835_PROPERTY(obj); - memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_property_ops, s, - TYPE_BCM2835_PROPERTY, 0x10); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); - sysbus_init_irq(SYS_BUS_DEVICE(s), &s->mbox_irq); -} - -static void bcm2835_property_reset(DeviceState *dev) -{ - BCM2835PropertyState *s = BCM2835_PROPERTY(dev); - - s->pending = false; -} - -static void bcm2835_property_realize(DeviceState *dev, Error **errp) -{ - BCM2835PropertyState *s = BCM2835_PROPERTY(dev); - Object *obj; - Error *err = NULL; - -<<<<<<< HEAD - obj = object_property_get_link(OBJECT(dev), "bcm2835_fb", &err); - if (obj == NULL) { - error_setg(errp, "%s: required bcm2835_fb link not found: %s", - __func__, error_get_pretty(err)); - return; - } - - s->fbdev = BCM2835_FB(obj); - - obj = object_property_get_link(OBJECT(dev), "dma_mr", &err); - if (obj == NULL) { - error_setg(errp, "%s: required dma_mr link not found: %s", -======= - obj = object_property_get_link(OBJECT(dev), "dma-mr", &err); - if (obj == NULL) { - error_setg(errp, "%s: required dma-mr link not found: %s", ->>>>>>> upstreaming-raspi - __func__, error_get_pretty(err)); - return; - } - - s->dma_mr = MEMORY_REGION(obj); - address_space_init(&s->dma_as, s->dma_mr, NULL); - - bcm2835_property_reset(dev); -} - -<<<<<<< HEAD -======= -static Property bcm2835_property_props[] = { - DEFINE_PROP_UINT32("ram-size", BCM2835PropertyState, ram_size, 0), - DEFINE_PROP_END_OF_LIST() -}; - ->>>>>>> upstreaming-raspi -static void bcm2835_property_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - -<<<<<<< HEAD -======= - dc->props = bcm2835_property_props; ->>>>>>> upstreaming-raspi - dc->realize = bcm2835_property_realize; - dc->vmsd = &vmstate_bcm2835_property; -} - -static TypeInfo bcm2835_property_info = { - .name = TYPE_BCM2835_PROPERTY, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2835PropertyState), - .class_init = bcm2835_property_class_init, - .instance_init = bcm2835_property_init, -}; - -static void bcm2835_property_register_types(void) -{ - type_register_static(&bcm2835_property_info); -} - -type_init(bcm2835_property_register_types) diff --git a/include/hw/arm/bcm2835_peripherals.h.orig b/include/hw/arm/bcm2835_peripherals.h.orig deleted file mode 100755 index 7fc9883a22..0000000000 --- a/include/hw/arm/bcm2835_peripherals.h.orig +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_PERIPHERALS_H -#define BCM2835_PERIPHERALS_H - -#include "qemu-common.h" -#include "exec/address-spaces.h" -#include "hw/sysbus.h" -<<<<<<< HEAD -#include "hw/char/bcm2835_aux.h" -#include "hw/display/bcm2835_fb.h" -#include "hw/dma/bcm2835_dma.h" -#include "hw/intc/bcm2835_ic.h" -#include "hw/misc/bcm2835_mphi.h" -#include "hw/misc/bcm2835_power.h" -#include "hw/misc/bcm2835_property.h" -#include "hw/misc/bcm2835_mbox.h" -#include "hw/sd/sdhci.h" -#include "hw/timer/bcm2835_st.h" -#include "hw/timer/bcm2835_timer.h" -#include "hw/usb/bcm2835_usb.h" - -#define TYPE_BCM2835_PERIPHERALS "bcm2835_peripherals" -======= -#include "hw/intc/bcm2835_ic.h" -#include "hw/misc/bcm2835_property.h" -#include "hw/misc/bcm2835_mbox.h" -#include "hw/sd/sdhci.h" - -#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" ->>>>>>> upstreaming-raspi -#define BCM2835_PERIPHERALS(obj) \ - OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS) - -typedef struct BCM2835PeripheralState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr; - MemoryRegion ram_alias[4]; - qemu_irq irq, fiq; - - SysBusDevice *uart0; -<<<<<<< HEAD - BCM2835AuxState aux; - BCM2835FbState fb; - BCM2835DmaState dma; - BCM2835ICState ic; - BCM2835MphiState mphi; - BCM2835PowerState power; - BCM2835PropertyState property; - BCM2835MboxState mboxes; - SDHCIState sdhci; - BCM2835StState st; - BCM2835TimerState timer; - BCM2835UsbState usb; -======= - BCM2835ICState ic; - BCM2835PropertyState property; - BCM2835MboxState mboxes; - SDHCIState sdhci; ->>>>>>> upstreaming-raspi -} BCM2835PeripheralState; - -#endif /* BCM2835_PERIPHERALS_H */ diff --git a/include/hw/arm/raspi_platform.h.orig b/include/hw/arm/raspi_platform.h.orig deleted file mode 100755 index c5ae5bb951..0000000000 --- a/include/hw/arm/raspi_platform.h.orig +++ /dev/null @@ -1,262 +0,0 @@ -/* - * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines - * -<<<<<<< HEAD - * These definitions are derived from those in Linux at - * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h - * where they carry the following notice: - */ - -/* - * arch/arm/mach-bcm2708/include/mach/platform.h -======= - * These definitions are derived from those in Raspbian Linux at - * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h - * where they carry the following notice: ->>>>>>> upstreaming-raspi - * - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -<<<<<<< HEAD -/* Peripheral base address on the VC (GPU) system bus */ -#define BCM2835_VC_PERI_BASE 0x7e000000 - -/* Peripheral base addresses seen by the CPU: Pi1 and Pi2 differ */ -#define BCM2835_PERI_BASE 0x20000000 -#define BCM2836_PERI_BASE 0x3F000000 - -/* "QA7" (Pi2) interrupt controller and mailboxes etc. */ -#define BCM2836_CONTROL_BASE 0x40000000 - -======= ->>>>>>> upstreaming-raspi -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device - * (the multicore sync block) */ -#define IC0_OFFSET 0x2000 -#define ST_OFFSET 0x3000 /* System Timer */ -#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ -#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ -#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) -#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ -#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores - * Doorbells & Mailboxes */ -#define PM_OFFSET 0x100000 /* Power Management, Reset controller - * and Watchdog registers */ -<<<<<<< HEAD -#define PCM_CLOCK_OFFSET 0x101098 /* PCM Clock */ -#define RNG_OFFSET 0x104000 /* Hardware RNG */ -#define GPIO_OFFSET 0x200000 /* GPIO */ -#define UART0_OFFSET 0x201000 /* Uart 0 */ -#define MMCI0_OFFSET 0x202000 /* MMC interface */ -#define I2S_OFFSET 0x203000 /* I2S */ -#define SPI0_OFFSET 0x204000 /* SPI0 */ -#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ -#define UART1_OFFSET 0x215000 /* Uart 1 */ -#define EMMC_OFFSET 0x300000 /* eMMC interface */ -#define SMI_OFFSET 0x600000 /* SMI */ -======= -#define PCM_CLOCK_OFFSET 0x101098 -#define RNG_OFFSET 0x104000 -#define GPIO_OFFSET 0x200000 -#define UART0_OFFSET 0x201000 -#define MMCI0_OFFSET 0x202000 -#define I2S_OFFSET 0x203000 -#define SPI0_OFFSET 0x204000 -#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ -#define UART1_OFFSET 0x215000 -#define EMMC_OFFSET 0x300000 -#define SMI_OFFSET 0x600000 ->>>>>>> upstreaming-raspi -#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ -#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */ -#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ - -<<<<<<< HEAD -/* - * Interrupt assignments - */ - -#define ARM_IRQ1_BASE 0 -#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) - -#define ARM_IRQ2_BASE 32 -#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) - -#define ARM_IRQ0_BASE 64 -#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -======= -/* GPU interrupts */ -#define INTERRUPT_TIMER0 0 -#define INTERRUPT_TIMER1 1 -#define INTERRUPT_TIMER2 2 -#define INTERRUPT_TIMER3 3 -#define INTERRUPT_CODEC0 4 -#define INTERRUPT_CODEC1 5 -#define INTERRUPT_CODEC2 6 -#define INTERRUPT_JPEG 7 -#define INTERRUPT_ISP 8 -#define INTERRUPT_USB 9 -#define INTERRUPT_3D 10 -#define INTERRUPT_TRANSPOSER 11 -#define INTERRUPT_MULTICORESYNC0 12 -#define INTERRUPT_MULTICORESYNC1 13 -#define INTERRUPT_MULTICORESYNC2 14 -#define INTERRUPT_MULTICORESYNC3 15 -#define INTERRUPT_DMA0 16 -#define INTERRUPT_DMA1 17 -#define INTERRUPT_DMA2 18 -#define INTERRUPT_DMA3 19 -#define INTERRUPT_DMA4 20 -#define INTERRUPT_DMA5 21 -#define INTERRUPT_DMA6 22 -#define INTERRUPT_DMA7 23 -#define INTERRUPT_DMA8 24 -#define INTERRUPT_DMA9 25 -#define INTERRUPT_DMA10 26 -#define INTERRUPT_DMA11 27 -#define INTERRUPT_DMA12 28 -#define INTERRUPT_AUX 29 -#define INTERRUPT_ARM 30 -#define INTERRUPT_VPUDMA 31 -#define INTERRUPT_HOSTPORT 32 -#define INTERRUPT_VIDEOSCALER 33 -#define INTERRUPT_CCP2TX 34 -#define INTERRUPT_SDC 35 -#define INTERRUPT_DSI0 36 -#define INTERRUPT_AVE 37 -#define INTERRUPT_CAM0 38 -#define INTERRUPT_CAM1 39 -#define INTERRUPT_HDMI0 40 -#define INTERRUPT_HDMI1 41 -#define INTERRUPT_PIXELVALVE1 42 -#define INTERRUPT_I2CSPISLV 43 -#define INTERRUPT_DSI1 44 -#define INTERRUPT_PWA0 45 -#define INTERRUPT_PWA1 46 -#define INTERRUPT_CPR 47 -#define INTERRUPT_SMI 48 -#define INTERRUPT_GPIO0 49 -#define INTERRUPT_GPIO1 50 -#define INTERRUPT_GPIO2 51 -#define INTERRUPT_GPIO3 52 -#define INTERRUPT_I2C 53 -#define INTERRUPT_SPI 54 -#define INTERRUPT_I2SPCM 55 -#define INTERRUPT_SDIO 56 -#define INTERRUPT_UART 57 -#define INTERRUPT_SLIMBUS 58 -#define INTERRUPT_VEC 59 -#define INTERRUPT_CPG 60 -#define INTERRUPT_RNG 61 -#define INTERRUPT_ARASANSDIO 62 -#define INTERRUPT_AVSPMON 63 - -/* ARM CPU IRQs use a private number space */ -#define INTERRUPT_ARM_TIMER 0 -#define INTERRUPT_ARM_MAILBOX 1 -#define INTERRUPT_ARM_DOORBELL_0 2 -#define INTERRUPT_ARM_DOORBELL_1 3 -#define INTERRUPT_VPU0_HALTED 4 -#define INTERRUPT_VPU1_HALTED 5 -#define INTERRUPT_ILLEGAL_TYPE0 6 -#define INTERRUPT_ILLEGAL_TYPE1 7 ->>>>>>> upstreaming-raspi diff --git a/include/hw/intc/bcm2835_ic.h.orig b/include/hw/intc/bcm2835_ic.h.orig deleted file mode 100755 index 49cb24e058..0000000000 --- a/include/hw/intc/bcm2835_ic.h.orig +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_IC_H -#define BCM2835_IC_H - -#include "hw/sysbus.h" - -<<<<<<< HEAD -#define TYPE_BCM2835_IC "bcm2835_ic" -======= -#define TYPE_BCM2835_IC "bcm2835-ic" ->>>>>>> upstreaming-raspi -#define BCM2835_IC(obj) OBJECT_CHECK(BCM2835ICState, (obj), TYPE_BCM2835_IC) - -#define BCM2835_IC_GPU_IRQ "gpu-irq" -#define BCM2835_IC_ARM_IRQ "arm-irq" - -typedef struct BCM2835ICState { - /*< private >*/ - SysBusDevice busdev; - /*< public >*/ - - MemoryRegion iomem; -<<<<<<< HEAD -======= - qemu_irq irq; - qemu_irq fiq; ->>>>>>> upstreaming-raspi - - /* 64 GPU IRQs + 8 ARM IRQs = 72 total (GPU first) */ - uint64_t gpu_irq_level, gpu_irq_enable; - uint8_t arm_irq_level, arm_irq_enable; - bool fiq_enable; - uint8_t fiq_select; -<<<<<<< HEAD - qemu_irq irq; - qemu_irq fiq; -======= ->>>>>>> upstreaming-raspi -} BCM2835ICState; - -#endif diff --git a/include/hw/intc/bcm2836_control.h.orig b/include/hw/intc/bcm2836_control.h.orig deleted file mode 100755 index a03587b9e4..0000000000 --- a/include/hw/intc/bcm2836_control.h.orig +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2836_CONTROL_H -#define BCM2836_CONTROL_H - -#include "hw/sysbus.h" - -/* 4 mailboxes per core, for 16 total */ -#define BCM2836_NCORES 4 -#define BCM2836_MBPERCORE 4 - -<<<<<<< HEAD -#define TYPE_BCM2836_CONTROL "bcm2836_control" -======= -#define TYPE_BCM2836_CONTROL "bcm2836-control" ->>>>>>> upstreaming-raspi -#define BCM2836_CONTROL(obj) \ - OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL) - -typedef struct BCM2836ControlState { - /*< private >*/ - SysBusDevice busdev; - /*< public >*/ - MemoryRegion iomem; - - /* interrupt status registers (not directly visible to user) */ - bool gpu_irq, gpu_fiq; -<<<<<<< HEAD - uint32_t localirqs[BCM2836_NCORES]; -======= - uint8_t localirqs[BCM2836_NCORES]; ->>>>>>> upstreaming-raspi - - /* mailboxes */ - uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE]; - - /* interrupt routing/control registers */ - uint8_t route_gpu_irq, route_gpu_fiq; - uint32_t timercontrol[BCM2836_NCORES]; - uint32_t mailboxcontrol[BCM2836_NCORES]; - - /* interrupt source registers, post-routing (visible) */ - uint32_t irqsrc[BCM2836_NCORES]; - uint32_t fiqsrc[BCM2836_NCORES]; - - /* outputs to CPU cores */ - qemu_irq irq[BCM2836_NCORES]; - qemu_irq fiq[BCM2836_NCORES]; -} BCM2836ControlState; - -#endif diff --git a/include/hw/misc/bcm2835_mbox.h.orig b/include/hw/misc/bcm2835_mbox.h.orig deleted file mode 100644 index 1561d17763..0000000000 --- a/include/hw/misc/bcm2835_mbox.h.orig +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_MBOX_H -#define BCM2835_MBOX_H - -#include "bcm2835_mbox_defs.h" -#include "hw/sysbus.h" -#include "exec/address-spaces.h" - -<<<<<<< HEAD -#define TYPE_BCM2835_MBOX "bcm2835_mbox" -======= -#define TYPE_BCM2835_MBOX "bcm2835-mbox" ->>>>>>> upstreaming-raspi -#define BCM2835_MBOX(obj) \ - OBJECT_CHECK(BCM2835MboxState, (obj), TYPE_BCM2835_MBOX) - -typedef struct { - uint32_t reg[MBOX_SIZE]; - uint32_t count; - uint32_t status; - uint32_t config; -} BCM2835Mbox; - -typedef struct { - /*< private >*/ - SysBusDevice busdev; - /*< public >*/ - MemoryRegion *mbox_mr; - AddressSpace mbox_as; - MemoryRegion iomem; -<<<<<<< HEAD - bool mbox_irq_disabled; - qemu_irq arm_irq; -======= - qemu_irq arm_irq; - bool mbox_irq_disabled; ->>>>>>> upstreaming-raspi - bool available[MBOX_CHAN_COUNT]; - BCM2835Mbox mbox[2]; -} BCM2835MboxState; - -#endif diff --git a/include/hw/misc/bcm2835_mbox_defs.h.orig b/include/hw/misc/bcm2835_mbox_defs.h.orig deleted file mode 100644 index 2755286bdd..0000000000 --- a/include/hw/misc/bcm2835_mbox_defs.h.orig +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_MBOX_DEFS_H -#define BCM2835_MBOX_DEFS_H - -/* Constants shared with the ARM identifying separate mailbox channels */ -#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ -#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ -#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ -#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ -#define MBOX_CHAN_COUNT 9 - -#define MBOX_SIZE 32 -#define MBOX_INVALID_DATA 0x0f - -/* Layout of the private address space used for communication between - * the mbox device emulation, and child devices: each channel occupies -<<<<<<< HEAD - * 16 bytes of address space, but only two registers are presently defined. */ -======= - * 16 bytes of address space, but only two registers are presently defined. - */ ->>>>>>> upstreaming-raspi -#define MBOX_AS_CHAN_SHIFT 4 -#define MBOX_AS_DATA 0 /* request / response data (RW at offset 0) */ -#define MBOX_AS_PENDING 4 /* pending response status (RO at offset 4) */ - -#endif /* BCM2835_MBOX_DEFS_H */ diff --git a/include/hw/misc/bcm2835_property.h.orig b/include/hw/misc/bcm2835_property.h.orig deleted file mode 100755 index 578e794de3..0000000000 --- a/include/hw/misc/bcm2835_property.h.orig +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_PROPERTY_H -#define BCM2835_PROPERTY_H - -#include "hw/sysbus.h" -#include "exec/address-spaces.h" -<<<<<<< HEAD -#include "hw/display/bcm2835_fb.h" - -#define TYPE_BCM2835_PROPERTY "bcm2835_property" -======= - -#define TYPE_BCM2835_PROPERTY "bcm2835-property" ->>>>>>> upstreaming-raspi -#define BCM2835_PROPERTY(obj) \ - OBJECT_CHECK(BCM2835PropertyState, (obj), TYPE_BCM2835_PROPERTY) - -typedef struct { - /*< private >*/ - SysBusDevice busdev; - /*< public >*/ - MemoryRegion *dma_mr; - AddressSpace dma_as; -<<<<<<< HEAD - BCM2835FbState *fbdev; - MemoryRegion iomem; - uint32_t addr; - bool pending; - qemu_irq mbox_irq; -======= - MemoryRegion iomem; - qemu_irq mbox_irq; - uint32_t ram_size; - uint32_t addr; - bool pending; ->>>>>>> upstreaming-raspi -} BCM2835PropertyState; - -#endif -- 2.11.4.GIT