From c672f19f328922eff4963b0b61fbdcfa661e1c06 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Thu, 7 Oct 2021 16:17:41 +0800 Subject: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v oprsz and maxsz are passed with the same value in commit: eee2d61e202. However, vmv.v.v was missed in that commit and should pass the same value as well in its tcg_gen_gvec_2_ptr() call. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20211007081803.1705656-1-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 081a5ca34d..45be491ed4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + cpu_env, s->vlen / 8, s->vlen / 8, data, + fns[s->sew]); gen_set_label(over); } return true; -- 2.11.4.GIT