From 9321c1f2d08817fdb90ad129fbe3194207e73ba0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 3 Sep 2020 17:31:04 +0200 Subject: [PATCH] hw/sd/sdhci: Yield if interrupt delivered during multiple transfer MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The Descriptor Table has a bit to allow the DMA to generates Interrupt when the operation of the descriptor line is completed (see "1.13.4. Descriptor Table" of 'SD Host Controller Simplified Specification Version 2.00'). If we have pending interrupt and the descriptor requires it to be generated as soon as it is completed, reschedule pending transfers and yield to the CPU. Signed-off-by: Philippe Mathieu-Daudé Tested-by: Alexander Bulekov Message-Id: <20200903172806.489710-5-f4bug@amsat.org> --- hw/sd/sdhci.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index b93ecefd20..2f8b74a84f 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -837,7 +837,10 @@ static void sdhci_do_adma(SDHCIState *s) s->norintsts |= SDHC_NIS_DMA; } - sdhci_update_irq(s); + if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { + /* IRQ delivered, reschedule current transfer */ + break; + } } /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ -- 2.11.4.GIT