From 7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Fri, 25 Apr 2014 08:39:48 -0700 Subject: [PATCH] xilinx_timer: Fix writes into TCSR register The TCSR register has only 11 valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias --- hw/timer/xilinx_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 6113b975bf..3ff1da9caf 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr, if (value & TCSR_TINT) value &= ~TCSR_TINT; - xt->regs[addr] = value; + xt->regs[addr] = value & 0x7ff; if (value & TCSR_ENT) timer_enable(xt); break; -- 2.11.4.GIT