From 620455350a8da7cc62ae82cb69dd5c556f744136 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 26 Mar 2019 17:27:17 +0800 Subject: [PATCH] target/riscv: Fix wrong expanding for c.fswsp base register is no rs1 not rs2 for fsw. Signed-off-by: Kito Cheng Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 5819f53f90..ebcd977b2f 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 /* C.FSWSP */ - arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp }; + arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp }; return trans_fsw(ctx, &a_fsw); #else /* C.SDSP */ -- 2.11.4.GIT