From 528dc354b6f3aa82d65141cc60bc0e725e6cae98 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 14 Feb 2020 11:46:43 -0800 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD INS Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b83d09dbcd..bd68588a71 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn, write_vec_element(s, tmp, rd, dst_index, size); tcg_temp_free_i64(tmp); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } @@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) idx = extract32(imm5, 1 + size, 4 - size); write_vec_element(s, cpu_reg(s, rn), rd, idx, size); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } /* -- 2.11.4.GIT