From 47bdec821b8dda7658e3e802a26b9bd8319cdb49 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Thu, 20 Jan 2022 20:20:36 +0800 Subject: [PATCH] target/riscv: Relax debug check for pm write Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9be2820d2b..c00a82022e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1556,6 +1556,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno) int csr_priv = get_field(csrno, 0x300); int pm_current; + if (env->debugger) { + return false; + } /* * If priv lvls differ that means we're accessing csr from higher priv lvl, * so allow the access -- 2.11.4.GIT