From 2d4ab117bebb90ad7e7e65629f99f9e82ba32053 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 13 Feb 2021 12:24:44 +0100 Subject: [PATCH] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-16-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/tx79.decode | 4 +++ target/mips/tcg/tx79_translate.c | 54 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 0f748b53a6..26c80b9bce 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -32,8 +32,12 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs # MMI2 PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd +PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd +PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd # MMI3 PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd +POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd +PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index ad83774b97..00364f10d4 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -2,6 +2,7 @@ * Toshiba TX79-specific instructions translation routines * * Copyright (c) 2018 Fredrik Noring + * Copyright (c) 2021 Philippe Mathieu-Daudé * * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -114,6 +115,35 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word */ +static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, + void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + /* Lower half */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + gen_logic_i64(cpu_gpr[a->rd], ax, bx); + + /* Upper half */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + /* * Min/Max (4 instructions) * ------------------------ @@ -139,6 +169,30 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PNOR rd, rs, rt Parallel NOR */ +/* Parallel And */ +static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_arith(ctx, a, tcg_gen_and_i64); +} + +/* Parallel Or */ +static bool trans_POR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_arith(ctx, a, tcg_gen_or_i64); +} + +/* Parallel Exclusive Or */ +static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); +} + +/* Parallel Not Or */ +static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); +} + /* * Shift (9 instructions) * ---------------------- -- 2.11.4.GIT