From 05d9d0359e6da7dc8255712d745d079a04fa5ae5 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 22 May 2021 20:16:15 +0200 Subject: [PATCH] target/mips: Do not abort on invalid instruction MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-2-f4bug@amsat.org> --- target/mips/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3fd0c48d77..4b7229a868 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) tcg_gen_lookup_and_goto_ptr(); break; default: - fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); - abort(); + LOG_DISAS("unknown branch 0x%x\n", proc_hflags); + gen_reserved_instruction(ctx); } } } -- 2.11.4.GIT