| commit | 0ab5953b00b3165877d00cf75de628c51670b550 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Mon, 8 Oct 2018 13:55:02 +0000 (8 14:55 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 8 Oct 2018 13:55:02 +0000 (8 14:55 +0100) | ||
| tree | b43d07ca452159efd4cbc70c4412cbca1c1ad79f | treesnapshot (tar.gz zip) |
| parent | 2de7ace292cf7846b0cda0e940272d2cb0e06859 | commitdiff |
target/arm: Handle SVE vector length changes in system mode
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register bits.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register bits.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/cpu64.c | diffblobblamehistory | |
| target/arm/helper.c | diffblobblamehistory | |
| target/arm/op_helper.c | diffblobblamehistory |