| commit | fadefada4d07a3a77c4171244cded0e9af81331c | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 25 Sep 2019 14:32:32 +0000 (25 16:32 +0200) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 15 Oct 2019 17:09:04 +0000 (15 18:09 +0100) | ||
| tree | 0ad3e577ea46c5dd89c86caf669d58d2597c6985 | treesnapshot (tar.gz zip) |
| parent | c20375dd8678eae2462a986938e6d119cb5abefa | commitdiff |
aspeed/timer: Add support for IRQ status register on the AST2600
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Modify the vmstate version to take into account the new fields.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-8-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Modify the vmstate version to take into account the new fields.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-8-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/timer/aspeed_timer.c | diffblobblamehistory | |
| include/hw/timer/aspeed_timer.h | diffblobblamehistory |