| commit | f6768aa1b4c6a80448eabd22bb9b4123c709caea | |
| author | Remi Denis-Courmont <remi.denis.courmont@huawei.com> | |
| Sat, 26 Jan 2019 06:52:10 +0000 (26 08:52 +0200) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 15:23:51 +0000 (1 15:23 +0000) | ||
| tree | 585951c8095ce4bd679387276a0739809cc28b7c | treesnapshot (tar.gz zip) |
| parent | 87877543b14feebf1bc4fd336d41901b036acf98 | commitdiff |
target/arm: fix AArch64 virtual address space size
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
extension (yet), the VA address space is 48-bits plus a sign bit. User
mode can only handle the positive half of the address space, so that
makes a limit of 48 bits.
(With LVA, it would be 53 and 52 bits respectively.)
The incorrectly large address space conflicts with PAuth instructions,
which use bits 48-54 and 56-63 for the pointer authentication code. This
also conflicts with (as yet unsupported by QEMU) data tagging and with
the ARMv8.5-MTE extension.
Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
extension (yet), the VA address space is 48-bits plus a sign bit. User
mode can only handle the positive half of the address space, so that
makes a limit of 48 bits.
(With LVA, it would be 53 and 52 bits respectively.)
The incorrectly large address space conflicts with PAuth instructions,
which use bits 48-54 and 56-63 for the pointer authentication code. This
also conflicts with (as yet unsupported by QEMU) data tagging and with
the ARMv8.5-MTE extension.
Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/cpu.h | diffblobblamehistory |