| commit | f31e8f1318384a680db7280f999c01ae3ef9591c | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Tue, 1 Sep 2020 12:21:50 +0000 (1 14:21 +0200) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Tue, 1 Sep 2020 12:21:50 +0000 (1 14:21 +0200) | ||
| tree | acce6e61e7cea80e5989efcc630e61ac798b3606 | treesnapshot (tar.gz zip) |
| parent | 9b9624714c979e05bb99065966c362b0315b490a | commitdiff |
aspeed/sdhci: Fix reset sequence
BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until
the bit is cleared by HW.
Use the number of supported slots to define the default value of this
register (The AST2600 eMMC Controller only has one). Fix the reset
sequence by clearing automatically the RESET bit.
Cc: Eddie James <eajames@linux.ibm.com>
Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until
the bit is cleared by HW.
Use the number of supported slots to define the default value of this
register (The AST2600 eMMC Controller only has one). Fix the reset
sequence by clearing automatically the RESET bit.
Cc: Eddie James <eajames@linux.ibm.com>
Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/sd/aspeed_sdhci.c | diffblobblamehistory |