| commit | ed0c37eedfdb953d61d1e0a41439cd404e914d9d | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Fri, 1 Dec 2017 16:06:01 +0000 (1 17:06 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Thu, 14 Dec 2017 22:49:24 +0000 (15 09:49 +1100) | ||
| tree | 6a6f66658e2acfa014a20f76f5c6ac350b61ca23 | treesnapshot (tar.gz zip) |
| parent | 4f7a47beebd6d37861d08c81941be1b33a0ae627 | commitdiff |
ppc/xics: assign of the CPU 'intc' pointer under the core
The 'intc' pointer of the CPU references the interrupt presenter in
the XICS interrupt mode. When the XIVE interrupt mode is available and
activated, the machine will need to reassign this pointer to reflect
the change.
Moving this assignment under the realize routine of the CPU will ease
the process when the interrupt mode is toggled.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The 'intc' pointer of the CPU references the interrupt presenter in
the XICS interrupt mode. When the XIVE interrupt mode is available and
activated, the machine will need to reassign this pointer to reflect
the change.
Moving this assignment under the realize routine of the CPU will ease
the process when the interrupt mode is toggled.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/intc/xics.c | diffblobblamehistory | |
| hw/ppc/pnv_core.c | diffblobblamehistory | |
| hw/ppc/spapr_cpu_core.c | diffblobblamehistory |