| commit | ebd205c0807a146bf272208f3d41728d5e985ceb | |
| author | Andrew Jeffery <andrew@aj.id.au> | |
| Mon, 1 Jul 2019 16:26:18 +0000 (1 17:26 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 1 Jul 2019 16:29:00 +0000 (1 17:29 +0100) | ||
| tree | 702207e57a92eddd1ffa13bcfd90635a69149da9 | treesnapshot (tar.gz zip) |
| parent | 118c82e7ff4bd3aeaeca31caa64fb95351531ac4 | commitdiff |
aspeed: vic: Add support for legacy register interface
The legacy interface only supported up to 32 IRQs, which became
restrictive around the AST2400 generation. QEMU support for the SoCs
started with the AST2400 along with an effort to reimplement and
upstream drivers for Linux, so up until this point the consumers of the
QEMU ASPEED support only required the 64 IRQ register interface.
In an effort to support older BMC firmware, add support for the 32 IRQ
interface.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-22-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The legacy interface only supported up to 32 IRQs, which became
restrictive around the AST2400 generation. QEMU support for the SoCs
started with the AST2400 along with an effort to reimplement and
upstream drivers for Linux, so up until this point the consumers of the
QEMU ASPEED support only required the 64 IRQ register interface.
In an effort to support older BMC firmware, add support for the 32 IRQ
interface.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-22-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/aspeed_vic.c | diffblobblamehistory |