| commit | eb3f4298c96d79a5a67b904c28f293864cc5ccc3 | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Mon, 18 Feb 2019 11:11:40 +0000 (18 03:11 -0800) | ||
| committer | Max Filippov <jcmvbkbc@gmail.com> | |
| Thu, 28 Feb 2019 12:43:22 +0000 (28 04:43 -0800) | ||
| tree | 5cb370d2454e556508d48b6cedbdf84a13558ff2 | treesnapshot (tar.gz zip) |
| parent | 068e538a54552289a58689f21c99ed3696e59961 | commitdiff |
target/xtensa: implement PREFCTL SR
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| target/xtensa/cpu.h | diffblobblamehistory | |
| target/xtensa/translate.c | diffblobblamehistory |