Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210211-1' into staging
target-arm queue:
* Correctly initialize MDCR_EL2.HPMN
* versal: Use nr_apu_cpus in favor of hard coding 2
* accel/tcg: Add URL of clang bug to comment about our workaround
* Add support for FEAT_DIT, Data Independent Timing
* Remove GPIO from unimplemented NPCM7XX
* Fix SCR RES1 handling
* Don't migrate CPUARMState.features
# gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210211-1:
target/arm: Correctly initialize MDCR_EL2.HPMN
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
accel/tcg: Add URL of clang bug to comment about our workaround
arm: Update infocenter.arm.com URLs
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
target/arm: Add support for FEAT_DIT, Data Independent Timing
hw/arm: Remove GPIO from unimplemented NPCM7XX
target/arm: Fix SCR RES1 handling
target/arm: Don't migrate CPUARMState.features
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>