| commit | eab0bdb07cbed1131be2d1f541059c7b96b05e32 | |
| author | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Tue, 23 Oct 2018 15:26:58 +0000 (23 17:26 +0200) | ||
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Mon, 29 Oct 2018 13:13:47 +0000 (29 14:13 +0100) | ||
| tree | ac7bdd7611cf5a0d253491b4220a733e4482d351 | treesnapshot (tar.gz zip) |
| parent | a031ac61619294ae473a78d1834e757fad8b59e5 | commitdiff |
target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| target/mips/translate.c | diffblobblamehistory |