| commit | ea8cfdb5d19af45f98abe02844c7963dafec6e92 | |
| author | Alex Williamson <alex.williamson@redhat.com> | |
| Wed, 12 Dec 2018 19:39:16 +0000 (12 12:39 -0700) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Wed, 19 Dec 2018 21:48:16 +0000 (19 16:48 -0500) | ||
| tree | 4a6054bf154d51588468f0344cf72e2ac9c49068 | treesnapshot (tar.gz zip) |
| parent | 4695a2c50076879000ddde9f80d07bbcacfa0f26 | commitdiff |
pcie: Add link speed and width fields to PCIESlot
Add fields allowing the PCIe link speed and width of a PCIESlot to
be configured, with an instance_post_init callback on the root port
parent class to set defaults. This allows child classes to set these
via properties or via their own instance_init callback, without
requiring all implementions to support arbitrary user selected values.
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Add fields allowing the PCIe link speed and width of a PCIESlot to
be configured, with an instance_post_init callback on the root port
parent class to set defaults. This allows child classes to set these
via properties or via their own instance_init callback, without
requiring all implementions to support arbitrary user selected values.
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| hw/pci-bridge/pcie_root_port.c | diffblobblamehistory | |
| include/hw/pci/pcie_port.h | diffblobblamehistory |