| commit | ea71258da4b8141d8a808d94518a0964c0f92810 | |
| author | Alexander Graf <agraf@suse.de> | |
| Sun, 19 Jan 2014 16:49:11 +0000 (19 17:49 +0100) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Mon, 16 Jun 2014 11:24:35 +0000 (16 13:24 +0200) | ||
| tree | 253b6f10663b08f0846bd40a08821501a15495dd | treesnapshot (tar.gz zip) |
| parent | d2ea2bf740c515de41f45e4d6f36683db3458881 | commitdiff |
PPC: Properly emulate L1CSR0 and L1CSR1
There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).
Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.
Signed-off-by: Alexander Graf <agraf@suse.de>
There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).
Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/cpu.h | diffblobblamehistory | |
| target-ppc/translate_init.c | diffblobblamehistory |