| commit | ea04dce7bb4ccd3e464e5189c0d6d53510b7c212 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Fri, 16 Oct 2020 21:07:54 +0000 (16 14:07 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 20 Oct 2020 15:12:00 +0000 (20 16:12 +0100) | ||
| tree | 0e323ac3696644738504bf4fcc895ab0c496f160 | treesnapshot (tar.gz zip) |
| parent | 3ab6e68cd035de244d9bf999900349a69939ad41 | commitdiff |
target/arm: Use tlb_flush_page_bits_by_mmuidx*
When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.
The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.
Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.
The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.
Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/helper.c | diffblobblamehistory |