| commit | e6bba2ef49670167694b227df13fc8461debbcd5 | |
| author | Nathan Froyd <froydnj@codesourcery.com> | |
| Tue, 23 Feb 2010 19:55:14 +0000 (23 11:55 -0800) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Sat, 27 Feb 2010 15:10:49 +0000 (27 16:10 +0100) | ||
| tree | 37d30bc9f4320bcf0ad0ae2fe1d6a7a1e0272019 | treesnapshot (tar.gz zip) |
| parent | e3b283e94acc6fc304cc54971ee74c5a445a96b6 | commitdiff |
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.
Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.
Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target-ppc/cpu.h | diffblobblamehistory |