| commit | de6b55cbda2a26fb8889c8a8b44c139d7e106dce | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Sat, 11 Jul 2020 09:58:22 +0000 (11 02:58 -0700) | ||
| committer | Max Filippov <jcmvbkbc@gmail.com> | |
| Fri, 21 Aug 2020 19:48:15 +0000 (21 12:48 -0700) | ||
| tree | 39226f6cfb491940e5f0b88fd1ff4f60bd6072e1 | treesnapshot (tar.gz zip) |
| parent | 5dbb4c96d50c6ef74d4fd71a5a0fd9763d5a3662 | commitdiff |
target/xtensa: add DFPU option
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| target/xtensa/cpu.h | diffblobblamehistory | |
| target/xtensa/overlay_tool.h | diffblobblamehistory |